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ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com march 2010 m9999-031810-1.2 ksz8692mpb/KSZ8692XPB register description revision 1.2 march 18, 2010
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 2 m9999-031810-1.2 general description the ksz8692mpb/KSZ8692XPB is a highly- integrated system-on-chip (soc) containing an arm 922t 32-bit processor and a rich set of peripherals to address the cost-sensitive, high-performance needs of a wide variety of high bandwidth networking and communications applications. features arm 922t high-performance processor core ? 250 mhz arm 922t risc processor core ? 8kb i-cache and 8kb d-cache ? configurable memory management unit (mmu) for linux and wince memory controller ? 8/16-bit external bus interface for flash, rom, sram, and external i/o ? nand flash controller with boot option ? 200mhz 32-bit ddr controller ? four jedec specification jesd82-1 compliant differential clock drivers for a glueless ddr interface solution ethernet interfaces ? two ethernet (10/100 mbps) macs ? mii interface ? fully compliant with ieee 802.3 ethernet standards pci interface ? version pci 2.3 ? 32-bit 33/66mhz ? integrated pci arbiter supports three external masters for ksz8692mpb and one external master for KSZ8692XPB ? configurable as host bridge or guest device ? glueless support for mini-pci or cardbus devices dual high-speed usb 2.0 interfaces ? two usb2.0 ports with integrated phy ? can be configured as 2- port host, or host + device sdio/sd host controller (for ksz8692mpb only) ? meets sd host contro ller standard specification version 1.0 ? meets sdio card specification version 1.0 dma controllers ? dedicated dma channels for pci, usb, sdio and ethernet ports peripherals ? four high-speed uart ports up to 5mbps ? two programmable 32-bit timers with watchdog timer capability ? interrupt controller ? twenty gpio ports ? one shared spi/i2c interface ? one i2s port debugging ? arm9 jtag debug interface ? jtag boundary scan support power management ? cpu and system clock speed step-down options ? ethernet port wake-on-lan ? ddr and pci power down operating voltage ? 1.2v power for core ? 3.3v power for i/o ? 2.5v power for ddr memory interface reference hardware and software evaluation kit ? hardware evaluation board ? board support package including firmware source codes, linux kernel, and software stacks ? complete hardware and software reference designs available
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 3 m9999-031810-1.2 revision history revision date summary of changes 1.0 10/20/08 new release 1.1 3/10/09 added spi operation, deleted amba bus 200 mhz support 1.2 3/2/2010 fix some typos
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 4 m9999-031810-1.2 contents 1.0 memory map .................................................................................................................................................... 5 2.0 register description ....................................................................................................................................... 6 2.1 register m ap summa ry ........................................................................................................... ......................... 6 2.2 pci-ahb bridge configuration r egisters (pabcsr) (0x2000-0x 3fff)........................................................ 10 2.3 ahb internal access to pci configur ation registers (o ffsets 0x2000- 0x20fc) ........................................... 18 2.4 ddr memory controller r egister (0x 4000-0x4 fff)................................................................................. ..... 31 2.5 static memory controller register (0 x5000-0x 5fff).............................................................................. ....... 58 2.6 wan dma register s (0x6000- 0x7fff) .............................................................................................. ........... 66 2.7 lan dma register s (0x8000- 0x9fff).............................................................................................. ............. 85 2.8 sdio registers (0xa000-0x afff) ................................................................................................. .............. 104 2.9 relation between transfer comple te and data ti meout e rror .................................................................... 124 2.10 relation between command complete and command tim eout error........................................................ 124 2.11 relation between command crc erro r and command tim eout error ...................................................... 124 2.12 error interrupt status enable/normal inte rrupt status enable r egister (o ffset 034h) ................................. 125 2.13 relation between auto cmd12 crc erro r and auto cmd12 timeout error .............................................. 129 2.14 capabilities regist er (offs et 040h) ............................................................................................ ................... 130 2.15 maximum current value definiti on table......................................................................................... ............ 132 2.16 usb registers (0xb000-0x dfff) .................................................................................................. .............. 133 2.17 capability r egister s ...................................................................................................................................... 148 2.18 operational regist ers .......................................................................................................... ......................... 148 2.19 uart registers (0xe000-0x e1ff) ................................................................................................. ............. 177 2.20 interrupt contro ller regi sters................................................................................................. ....................... 184 2.21 timer regi sters................................................................................................................ ............................. 212 2.22 gpio regi sters................................................................................................................. ............................ 214 2.23 i2c regi sters ................................................................................................................. .............................. 218 2.24 spi regi sters .................................................................................................................. .............................. 222 2.25 miscellaneous r egister s............................................................................................................................... 227 2.26 i2s regi sters .................................................................................................................. .............................. 230 2.27 sta regi sters.................................................................................................................. ............................. 232 2.28 mib count ers ................................................................................................................... ............................. 236 2.29 nand flash control regi sters (0x0000 - 0x ffff) ................................................................................. ...... 239 3.0 host communication .................................................................................................................................. 247 3.1 descriptor lists and data buffers .............................................................................................. ................... 247 3.2 receive descriptors (rdes0- rdes3).............................................................................................. ........... 247 3.3 transmit descriptors (tdes0-t des3)............................................................................................. ............ 250
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 5 m9999-031810-1.2 1.0 memory map upon power up, ksz8692mpb/KSZ8692XPB memory map is configured as shown below. the default base address for the ksz8692mpb/KSZ8692XPB system configuration register s is 0x1fff_0000. after power up, user is free to remap the memory for spec ific application by changing the corresponding base address. nand flash memory bank 0 64kb ddr 256mb system config. registers 64kb 0x0fff_ffff | | | | 0x0000_0000 0x1ffe_ffff | 0x1ffe 0000 0x1fff_ffff | 0x1fff_0000 total address space = 512mb reserved 256kb 0x1ffb_ffff 0x1ff8_0000
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 6 m9999-031810-1.2 2.0 register description this chapter describes the system configur ation registers(scrs) of the ksz8692mpb/KSZ8692XPB. 2.1 register map summary the ksz8692mpb/KSZ8692XPB scrs are located in a block of 64 kb in the host memory address space. after power on reset, user can remap the scr?s to a desired offset. t he scrs are word aligned, 32 bits long, and must be accessed using word instructions. within the 64kb, the address range for different function blocks is summarized in the following. 2.1.1 ahb (register offset) address map 0x0000 ? 0x1fff system registers 0x2000 ? 0x3fff pci bridge registers 0x4000 ? 0x4fff ddr memory controller registers 0x5000 ? 0x5fff static memory controller registers 0x6000 ? 0x7fff wan dma registers 0x8000 ? 0x9fff lan dma registers 0xa000 ? 0xafff sdio registers 0xb000 ? 0xbfff usb device controller registers 0xc000 ? 0xcfff usb host controller ehci registers 0xd000 ? 0xdfff usb host controller ohci register 0xe000 ? 0xffff peripheral registers (see apb addr ess mapping section for detailed mapping) 2.1.2 apb (register offset) address map 0xe000 ? 0xe07f uart 1 0xe080 ? 0xe0ff uart 2 0xe100 ? 0xe17f uart 3 0xe180 ? 0xe1ff uart 4 0xe200 ? 0xe3ff interrupt controller registers 0xe400 ? 0xe5ff timer controller registers 0xe600 ? 0xe7ff gpio controller registers 0xe800 ? 0xe8ff i2c registers 0xe900 ? 0xe9ff spi registers 0xea00 ? 0xeaff miscellaneous registers 0xeb00 ? 0xebff i2s registers 0xec00 ? 0xecff mdio registers 0xed00 ? 0xedff mib registers 0xef00 ? 0xefff undefined 2.1.3 system register (0x0000-0x1fff) 2.1.4 system configuration register (syscfg offset 0x0000) this register determines the start address of all the system control registers. the total system control register space is fixed at 64kbytes boundary.) the following table shows the register bit fields. bit field default value read/ write description 31:29 0x0 ro reserved 28:16 0x1fff rw sprbp system configuration register bank base pointer the base address of the system configur ation register bank. the resolution of the address is 64kbytes. 15:0 0x0 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 7 m9999-031810-1.2 2.1.5 system clock and bus control register (clkcon offset 0x0004) the clkcon register is written by the cpu to configure the running frequency of the cp u clock, system clock and ddr memory clock. the following table shows the clkcon register bit fields. bit field default value read/ write description 31:11 0x0 reserved 10:9 0x1 rw factory reserved 01 = (default) 8 0 rw sfmode system fast mode for simulation this bit is for simulation only. software should never set this bit. 7 0x0 rw pci66msel pci bus clock select when set, pci bus is running at 66 mhz. when cleared, pci bus is running at 33 mhz. 6:4 0x4 rw armcs arm9 clock select 100 = 250 011 = 200 010 = 166 (default) 001 = 125 000 = 50 3:2 0x3 rw dmcs ddr memory clock select 11 = 200 mhz 10 = 166 mhz 01 = 125 mhz (default) 00 = 100 mhz 1:0 0x2 rw scdc amba system clock ( sysclk) select 11 = reserved 10 = 166 mhz 01 = 125 mhz (default) 00 = 50 mhz 2.1.6 nand flash configuration register (nflcfg offset 0x0008) this register determines nand flash write protection, auto-page enable, and the start address of nand flash bank. the following table shows the register bit fields. bit field default value read/ write description 31 1 rw wpe_n write protection enable when set, nand flash memory write protect is off. when cleared, nand flash memory write protect is on. the write protect input to nand flash memory is controlled by this vaule 30 strapped by power-on reset rw apoe auto page open enable when set, auto page open function is enable when cleared, auto page open function is disable 29 0x0 ro reserved 28:16 0x1ffe rw nandflbp register bank base pointer the base address of the nand flash bank . the resolution of the address is 64kbytes. 15:0 0x00 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 8 m9999-031810-1.2 2.1.7 factory reserved (offset 0x000c) 2.1.8 (factory reserved offset 0x0010) 2.1.9 ddr delay line and combo i/o pad configuration register (ddlcp offset 0x0014) the register is for the ddr delay line c onfiguration and i/o pad configuration. the following table shows the register bit fields. bit field default value read/ write description 31 0x0 ro byp_syspll bypass system pll enable: when set, the system pll is disabled and the clock input from xi has to be either 250 mhz or 200 mhz. the following lists out the clock rate for each clock domain when the system pll bypass is enabled. byp_syspll = 1 byp_syspll = 1 byp_clksel = 1 byp_clksel = 0 xi 250mhz 200mhz arm9 250mhz 200mhz denali 125mhz 200mhz pci n/a 66mhz rgmii 125mhz n/a sysclk 125mhz 100mhz note: this bit is configured from power strapping only. 30 0x0 ro byp_clksel bypass system pll clock select: (power strapping) when this bit is set and system pll is bypassed, the xi is expected to be 250 mhz. when this bit is cleared and sy stem pll is bypassed, the xi is expected to be 200 mhz. note: this bit is configured from power strapping only. 29:20 0x0 ro reserved 19:16 0xf rw ddrclken ddr memory clock output enable: when set, the corresponding ddr clock is enabled. when cleared, the corresponding ddr clock is forced at low. ddrclken[0] configures ddclko0 ddrclken[1] configures ddclko1 ddrclken[2] configures ddclko2 ddrclken[3] configures ddclko3 15:12 0x0 ro reserved 11 0x0 rw byp_dspll bypass deskew pll enable: when set, deskew pll is disabled in ddr clock adjustment. when cleared, deskew pll is used in ddr clock adjustment. 10 0x0 ro reserved 9:8 0x1 rw byp_dspll_dsel bypass deskew pll delay line select: 00: 1 mux(clkmx2x12) + 1 delay cell(dly4x4) delay 01: 1 mux(clkmx2x12) + 2 delay cell(dly4x4) delay 10: 1 mux(clkmx2x12) + 3 delay cell(dly4x4) delay 11: 1 mux(clkmx2x12) + 4 delay cell(dly4x4) delay
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 9 m9999-031810-1.2 7:4 0x1 rw ddln_sel ddr delay line configuration 0000: 2 mux(clkmx2x12) + 6 buf(clkbufx16) delay 0001: 2 mux(clkmx2x12) + 8 buf(clkbufx16) delay 0010: 4 mux(clkmx2x12) + 6 buf(clkbufx16) delay 0011: 4 mux(clkmx2x12) + 11buf(clkbufx16) delay 0100: 4 mux(clkmx2x12) + 12 buf(clkbufx16) delay 0101: 4 mux(clkmx2x12) + 13 buf(clkbufx16) delay 0110: 4 mux(clkmx2x12) + 14 buf(clkbufx16) delay 0111: 4 mux(clkmx2x12) + 15 buf(clkbufx16) delay 1000: 4 mux(clkmx2x12) + 16 buf(clkbufx16) delay 1001: 4 mux(clkmx2x12) + 17 buf(clkbufx16) delay 1010-1111: not valid 3 0x0 ro reserved 2 0x0 rw cmbo_pwd ddr pad (pwd) receiver power down enable (active high) 1:0 0x0 ro reserved 2.1.10 feature enable control registers (fec offset 0x0018) this register is for cpu to enable or disable the i/o channels or the security features. if the channel is disabled, the clock to the corresponding functional block will be shut off for power saving. the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 17 0 rw lpsleep wan port disable 16 0 rw wpsleep wan port sleep 15 0x0 rw tmdis timer interface disable 14 0x0 rw spidis spi(i2c) interface disable 13 0x0 rw i2sdis i2s interface disable 12 0x0 rw uart4dis uart4 interface disable 11 0x0 rw uart3dis uart3 interface disable 10 0x0 rw uart2dis uart2 interface disable 9 0x0 rw uart1dis uart1 interface disable 8 0x0 rw norfmdis nor flash memory disable 7 0x0 rw nandfmdis nand flash memory disable 6 0x0 rw pcidis pci interface disable 5 0x0 rw factory reserved 4 0x0 rw lpdis lan port disable 3 0x0 rw wpdis wan port disable 2 0x0 rw sdifdis sdio interface disable 1 0x0 rw usbddis usb device disable 0 0x0 rw usbhdis usb host disable
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 10 m9999-031810-1.2 2.1.11 nor flash / external i/o base address register (nfeioba offset 0x001c) this register determines the start address of stat ic memory nor flash/sram/rom and extrenal i/o banks the following table shows the register bit fields. bit field default value read/ write description 31:26 0x1fff rw nfeiobp nor flash ? external i/o bank base pointer the base address of the static memory and extrenal i/o banks. the resolution o f the address is 64mbytes. 25:0 0x0 ro reserved 2.2 pci-ahb bridge configuration registers (pabcsr) (0x2000-0x3fff) the pci-ahb bridge (pab) implements all c onfiguration registers required by the pc i specification. these registers are described in the following subsections. since the configur ation registers can be accessed from both the pci and ahb buses, they have two sets of addresses, one for each bus: pci and ahb. the pci bus configuration register address range is 0x0000-0x00fc, and the ahb bus configur ation register address range is 0x2000-0x20fc. the pab enables a full software-driven initialization and confi guration when acting as a host bridge. this allows the software to identify and query the pab. in the guest bridge m ode, the csid configuration register (subsystem id and subsystem vendor id) is programmed by the arm9, and the remaining configurat ion registers are programmed by the host system. the pab treats configuration space write operations to registers that are rese rved as no-ops. that is, the access completes normally on the bus and the data is discarded. r ead accesses, to reserved or unimplemented registers, complete normally and a data value of 0 is returned. software reset has no effect on the configuration registers. hard ware reset sets the configuration registers to their default values. the configuration register csid (subs ystem id and subsystem vendor id) is programmed by the arm9 during stage 1 initilization, thus eliminating the need for an eeprom. also, cbma[3] (prefetchable bit) can be initialized in stage 1. only internal access to these registers are done in stage 1 using offset range 0x2000-0x20fc; i.e., arm9 accesses does not propagate out to the pci bus. during stage 2 initialization, the arm9 programs the remain ing configuration registers by using the indirect registers pbca ( address register at offset 0x2100) and pbcd (data register at offset 0x2104). the arm9 programs the system control registers (csrs) located at offsets 0x2200-0x2224. the pci-ahb bridge csrs are locat ed in the host memory address space. the pbcsrs are word aligned, 32 bits long, and must be accessed using word instructions with word-aligned addresses only. note: reserved bits should be written with 0. failing to do this could cause incompatibility problems with a future version of the pci-ahb bridge. reserved bits are undefined on r ead access. retries on second data transactions occur in response to burst accesses. pbcsrs are physically located in the chip. the hos t uses a single instruction to access a csr.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 11 m9999-031810-1.2 the pci-ahb bridge implement the following configuraion r egisters and csr registers. t hese registers are described below. configuration register identifier pci bus address default value identification cfid 0x0000 0x869216c6 command and status cfcs 0x0004 0x04400000 revision cfrv 0x0008 0x06**0000 latency timer cflt 0x000c 0x00000000 configuration base memory address cbma 0x0010 0x00000000 reserved 0x0014-28 0x00000000 subsystem id csid 0x002c 0x******** reserved 0x0030-38 0x00000000 interrupt cfit 0x003c 0x00000100 reserved 0x0040-fc 0x00000000 register identifier ahb bus address default value configuration register: ident ification crcfid 0x2000 0x869216c6 configuration register: comm and and status crcfcs 0x2004 0x04400000 configuration register: re vision crcfrv 0x2008 0x06**0000 configuration register: lat ency timer crcflt 0x200c 0x00000000 configuration register : configuration base memory address crcbma 0x2010 0x00000000 reserved 0x2014-28 0x00000000 configuration register: subs ystem id crcsid 0x202c 0x******** reserved 0x2030-38 0x00000000 configuration register: in terrupt crcfit 0x203c 0x00000100 reserved 0x2040-fc 0x00000000 pci-ahb bridge configuration address pbca 0x2100 0x00000000 pci-ahb bridge configuration data pbcd 0x2104 0x00000000 pci-ahb bridge mode pbm 0x2200 0x00000000 pab-ahb bridge control and status pbcs 0x2204 0x00000000 pci-ahb bridge memory base address pmba 0x2208 0x00000000 pci-ahb bridge memory base a ddress control pmbac 0x220c 0x00000000
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 12 m9999-031810-1.2 pci-ahb bridge memory base address mask pmbam 0x2210 0x00000000 pci-ahb bridge memory base address translation pmbat 0x2214 0x00000000 pci-ahb bridge i/o base address pioba 0x2218 0x00000000 pci-ahb bridge i/o base address control piobac 0x221c 0x00000000 pci-ahb bridge i/o base address mask piobam 0x2220 0x00000000 pci-ahb bridge i/o base address translation piobat 0x2224 0x00000000 2.2.1 configuration id register (cfid pci offset 0x0000) the cfid register identif ies the pci-ahb bridge. the following table shows the cfid register bit fields. bit field default value read/ write description 31:16 0x8692 ro device id provides the unique pci-ahb bridge id number 15:0 0x16c6 ro vendor id specifies the manufacturer of the pci-ahb bridge 2.2.2 command and status configuration register (cfcs pci offset 0x0004) the cfcs register is divided into two sections: a command register (cfcs[15:0]) and a stat us register (cfcs[31:16]). the command register provides control of the pci-ahb br idge?s ability to generate and respond to pci cycles. when 0 is written to this register, the pc i-ahb bridge logically disconnects from the pci bus for all accesses except configuration accesses. the status register records status info rmation for the pci bus-related events. t he cfcs status bits are not cleared when they are read. writing 1 to these bits clears them; writing 0 has no effect. the following table describes the cfcs register bit fields. bit field type default value read/ write description 31 status 0 read/ clear detected parity error this bit is set when the bridge detec ts a parity error, even if parity error handling is disabled (as controlled by bit 6 in the command register). 30 status 0 read/ clear signal system error when set, indicates that the pci-ahb bridge asserted the system error serr_n pin. 29 status 0 read/ clear received master abort when set, indicates that the pci-ahb bridge terminated a master transaction (except for special cycle) with master abort. 28 status 0 read/ clear received target abort when set, indicates that the pci-ahb bridge master transaction was terminated due to a target abort. 27 status 0 read/ clear generated target abort when set, indicates that the pci-ahb bridge pci target generated a target abort.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 13 m9999-031810-1.2 26:25 status 10 ro device select timing these bits encode the timing of devsel#. three allowable timings for assertion of devsel#: 00 ? fast 01 ? medium 10 ? slow 24 status 0 read/ clear data parity report this bit is set when the following 3 conditions are met: 1) the bus agent asserted perr# itself (on a read) or observed perr# asserted (on a write) 2) the pci-ahb bridge operates as a bus master for the operation that c aused the error. 3) the parity error response bit (cfcs[6]) is set. 23:22 reserved 00 reserved 21 status 1 ro 66 mhz capable this read only bit indicates that the pci-ahb bridge is 66 mhz capable. its value is always set to 1. 20 status 1 ro new capability new capabilities are not implemented. 19:16 status 0x0 reserved 15:11 command 0x00 reserved 10 command 0 r/w interrupt disable this bit disables the device/function from asserting intx#. a value o f 0 enables the assertion of its intx# signal. a value of 1 disables the assertion of its intx# signal. this bit?s state after rst# is 0. 9 command 0 ro master fast back-to-back capable master cannot do fast back-to-back transactions to different devices. 8 command 0 r/w system error enable enable bit for serr# driver. a value of 0 disables the serr# driver. a value of 1 enables the serr# driver. this bit?s state after rst# is 0. address parity errors are reported only if this bit and bit 6 are 1. 7 command 0 ro address/data stepping bridge does not do addr ess/data stepping. 6 command 0 rw parity error response when set, the bridge takes its normal action when a parity error is detected. when the bit is 0, the bridge sets its detected parity error status bit (cfcs[31]) when an error is detected, but does not assert perr# and continues normal operation. this bit?s state after rst# is 0. 5 command 0 ro vga palette access vga palette snooping is disabled. 4 command 0 rw memory write and invalidate enable when set, the pci-ahb bridge is allowed to generate the memory write and invalidate command. when reset, the pci-ahb bridge can only generate memory write command. this bit?s state after rst# is 0. 3 command 0 ro special cycles response bridge ignores all special cycle operations.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 14 m9999-031810-1.2 2 command 0 rw master operation when set, the pci-ahb bridge is capable of acting as a bus master. when reset, the pci-ahb bridge capability to generate pci accesses is disabled. for normal operation, this bit must be set. this bit?s state after rst# is 0. 1 command 0 rw memory space access when set, the pci-ahb bridge responds to memory space accesses. when reset, the pci-ahb bridge does not respond to memory space accesses. this bit?s state after rst# is 0. 0 command 0 rw i/o space access when set, the pci-ahb bridge re sponds to i/o space accesses. when reset, the pci-ahb bridge does not respond to i/o space accesses. this bit?s state after rst# is 0. 2.2.3 configuration revision register (cfrv offset pci 0x0008) the cfrv register contains t he pci-ahb bridge revision number. the following table shows the cfrv register bit fields. bit field default value read/ write description 31:24 0x06 ro base class indicates device is a bridge, and is equal to 0x06. 23:16 - ro subclass. host/guest mode determined by input pin phgm. 0x00 ? in host bridge mode 0x80 ? in guest bridge mode 15:8 0x00 ro reserved 7:4 0x0 ro revision number indicates the pci-ahb bridge revision number, and is equal to 0h. this number is incremented for subsequent revision. 3:0 0x0 ro step number indicates the pci-ahb bridge step number , and is equal to 0h (chip revision a). this number is incremented for subsequent pci-ahb bridge steps within the current revision. 2.2.4 configuration latency timer register (cflt pci offset 0x000c) this register configures the cache line size field and the latency timer. the following table shows the cflt register bit fields. bit field default value read/ write description 31:16 0x0000 ro reserved 15:8 0x00 r/w configur ation latency timer specifies, in units of pci bus clocks, the value of the latency timer of the pci-ahb bridge. when the pci-ahb bridge asse rts frame_n, it enables its latency timer to count. if the pci-ahb bridge deasserts frame_n prior to count expiration, the content of the latency timer is ignored. otherwise, after the count expires, the pci-ahb bridge initiate s transaction termination as soon as its gnt_n is deasserted.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 15 m9999-031810-1.2 7:0 0x00 r/w cache line size specifies, in unit of 32-bit words(dword), t he system cache line size. the pci-ahb bridge supports cache line sizes of 4, 8, and 16 dwor ds. if an attempt is made to write an unsupported value to this register, the write is ignor ed and the pci-ahb bridge does not use the mwi command. if a value other than 8, 16 or 32 is wr itten to the register, the pci-ahb bridge returns all zeros when the register is read. the driver should use the value of the cache line size to progr am the cache alignment bits (csr0[15:14]). the pci-ahb bridge uses the cache alignment bits for pci commands that are cache oriented, such as memory-read-line, memory-read-multiple and memory-write-and- invalidate. 2.2.5 configuration base memory address (cbma pci offset 0x0010) the cbma register specify the base memory address for accessing the devices on the ahb. this register must be initialized prior to accessing any ahb device with memory access. the following table shows the cbma register bit fields. bit field default value read/ write description 31:28 0xfc r/w configuration base memory address defines the pci memory base address used to access pab and ahb resources. the resources reside in a 256mb address range. 27:4 0x0 reserved. 3 0 ro prefetchable 1 ? indicates memory space is prefetchable. 0 ? indicates memory space is not prefetchable. 2:1 00 ro type locate anywhere in 32-bit address space. 0 0 ro memory space indicator determines that the register maps into the memory space. the value in this field is 0. 2.2.6 configuration base address (pci offsets 0x0014-0x0028) these configuration base addre ss registers are reserved. bit field default value read/ write description 31:0 0x0 reserved. 2.2.7 subsystem id register (csid pci offset 0x002c) the csid register is a read-only 32-bit register. the content of the csid is loaded from the local cpu after a hardware reset. if the csid is accessed by the pci host before its content is loaded from the loca l cpu, the pci-ahb bridge responds with retry termination on the pci bus. the following table shows the csid register bit fields. bit field default value read/ write description 31:16 - ro subsystem id indicates a 16-bit field containing the subsystem id. 15:0 - ro subsystem vendor id indicates a 16-bit field containing the subsystem vendor id.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 16 m9999-031810-1.2 the following table shows the a ccess rules of the register. category description value after hardware reset arm9 cpu must progr am the value for subsystem id and subsystem vendor id during stage 1 pow er up configuration. write access rules only arm9 cpu can progr am the subsystem id and subsystem vendor id. this register is read-only on the pci bus. 2.2.8 capabilities pointer register (ccap offset 0x0034) the ccap register points to the base address of the power management register block in the configuration address space. this pointer is valid only if the new capabilities bit in cfcs is set. the following table shows the ccap register bit fields. read only. bit field default value description 31:8 000000h reserved. 7:0 50 capabilities pointer points to the location of the power management register block in the pci configuration space. the va lue of this field is 50h. 2.2.9 configuration interrupt register (cfit pci offset 0x003c) the cfit register is divided into two sections: the interrupt line and the interrupt pin. cfit configures both the system?s interrupt and the pci-ahb brid ge interrupt pin connection. the following table shows the cfit register bit fields. bit field default value read/ write description 31:24 0x00 ro max_lat this field indicates how often the device needs to gain access to the pci bus. time unit is equal to 0.25 us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 28h (10 us). 23:16 0x00 ro min_gnt this field indicates the burst period length that the device needs. time unit is equal to 0.25us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 14h (5 us). 15:8 0x01 ro interrupt pin indicates which interrupt pin that the pc i-ahb bridge uses. the pci-ahb bridge uses inta# and the read value is 01h. 7:0 0x00 r/w interrupt line provides interrupt line routing information. the basic i/o system (bios) writes the routing information into to this field when it initialized and confi gures the system. the value in this field indicates which i of t he system interrupt controller is connected to the pci-ahb bridge?s interrupt pin. the dr iver can use this information to determine priority and vector information. values in this field are system architecture specific.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 17 m9999-031810-1.2 2.2.10 capabilities id register (ccid offset 0x0050) the ccid register is a read-only register that provides information on the ksz8692mpb/KSZ8692XPBp power management capabilities. the following table shows the ccid register bit fields. read only . bit field default value description 31 0 pme support d3(cold) if this bit is set, the ksz8692mpb/KSZ8692XPBp asserts pme in d3(cold) power state. otherwise, the ksz 8692mpb/KSZ8692XPBp does not assert pme in d3(cold). here this bit is set. 30 1 pme support d3(hot) the value of this bit is 1, indicating that the ksz8692mpb/KSZ8692XPBp may assert pme in d3(hot) power state. 29 0 pme support d2 ksz8692mpb/KSZ8692XPBp does not assert pme in d2 state. 28 0 pme support d1 ksz8692mpb/KSZ8692XPBp does not assert pme in d1 state. 27 0 pme support d0 the value of this bit is 0, indi cating that the ksz 8692mpb/KSZ8692XPBp does not assert pme in d0 power state. 26 1 d2 support ksz8692mpb/KSZ8692XPBp support d2 power state. 25 1 d1 support ksz8692mpb/KSZ8692XPBp support d1 power state. 24:22 000 auxiliary current this 3-bit field reports the 3.3vaux auxiliary current requirements for the pci function. if pme# generation from d3_cold is not suppor ted by the function, this field must return a value of 000 when read. 21 0 device specific initialization indicates whether special init ialization of this function is required (beyond the standard pci configuration header) befor e the generic class device driver is able to use it. note that this bit is not used by some operating systems. microsoft windows and windows nt, for instance, do not use this bit to determine whether to use d3. instead, they use the driver?s capabilities to determine this. a ?1? indicates that the function require s a device specific initialization sequence following transition to the d0 uninitialization state. 20 0 reserved, should be set to 0. 19 1 pme clock when this bit is a ?1?, it indicates that the function relies on t he presence of the pci clock for pme# operation. when this bit is a ?0?, it indicates that no pci clock is required for the function to generate pme#. 18:16 3h power management pci version(1.2) the value of this bit is 3?b011 15:8 00h next item pointer points to the location of the next bl ock of the capabilities list in the pci configuration space. the value of this fi eld is 00h, indicating that this is the last item of the capability linked list. 7:0 01h capabilities id pci power management registers id. the value of this field is 01h, indicating that this is the power-m anagement register block.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 18 m9999-031810-1.2 2.2.11 power-management control and status register (cpmc offset 0x0054) the ccid register is a read-only register that provides information on the k8842 power management capabilities. the following table shows the ccid register bit fields. bit field default value description 31:16 0000h reserved. 15 0(ro, w1c) pme_status this bit indicates that the ksz 8692mpb/KSZ8692XPBp has det ected a power- management event. if bit pme_enable is set, the ksz8692mpb/KSZ8692XPBp also asserts the pme_n pin. this bit is cleared on power-up reset or by write 1. it is not modified by either hardware or software reset. when this bit is cleared, the ksz8692mpb/KSZ8692XPBp deassert s the pme_n pin. 14:9 00h reserved. 8 0(r/w) pme_enable if this bit is set, the ksz8692mpb/ksz 8692xpbp can assert the pme_n pin. otherwise, assertion of the pme_n pin is disabled. this bit is cleared on power-up reset only and is not modified by either hardware or software reset. 7:4 0h reserved. 3 1(ro) no soft reset if this bit is set (?1?), the ksz8692m pb/KSZ8692XPBp does not perform an internal reset when transitioning from d3_hot to d0 because of powerstate commands. configuration context is pres erved. upon transition from d3_hot to the d0 initialized state, no additional operating syst em intervention is required to preserve configuration context beyond writing the powerstate bits. if this bit is cleared (?0?), the ksz 8692mpb/KSZ8692XPBp does perform an internal reset when transitioning from d3_hot to d0 via software control of the powerstate bits. configuration context is lost w hen performing the soft reset. upon transition from d3_hot to the d0 state, full rein itialization sequence is needed to return the device to d0 initialized. regardless of this bit, devices that transiti on from d3_hot to d0 by a system or bus segment reset will return to the device st ate d0 uninitialized with only pme context preserved if pme is supported and enabled. 2 0 reserved. 1:0 00(rw) power state this field is used to set the curr ent power state of the ksz8692mpb/KSZ8692XPBp and to determine its power state. the definitions of t he field values are: 0: d0 1: d1 2: d2 3: d3(hot) this field gets a value of 0 after power up. 2.3 ahb internal access to pci confi guration registers (offsets 0x2000-0x20fc) the pci configuration registers can be accessed internally by the arm9 cpu using t he address offsets 0x2000-20fc. they are physically the same register s as the pci configuration registers, but accessing this address range will not generate pci configuration cycles on the pci bus. the only method arm9 can generate pci configuration cycles on the pci bus is through the indirect register s, configuration address (pbca) and conf iguration data (pbcd). during first stage initialization on power-up, the local cpu programs t he subsystem id and subsyste m vendor id configuration registers normally programmed by the eeprom. the followi ng sections describe the pci configuration registers described earlier with the difference being in the write access of t he register bits. all register bits are read-only except for the subsystem id and subsystem vendor id which are read/write.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 19 m9999-031810-1.2 2.3.1 configuration id register (crcfid offset 0x2000) the cfid register identif ies the pci-ahb bridge. the following table shows the cfid register bit fields. bit field default value read/ write description 31:16 0x8692 ro device id provides the unique pci-ahb bridge id number 15:0 0x16c6 ro vendor id specifies the manufacturer of the pci-ahb bridge. 2.3.2 command and status configuration register (crcfcs pci offset 0x2004) the crcfcs register is divided into two sections: a command regi ster (crcfcs[15:0]) and a status register (crcfcs[31:16]). the command register provides control of the pci-ahb bridge?s ability to generate and respond to pci cycles. the status register records status info rmation for the pci bus-related events. the crcfcs status bits are not cleared when they are read. the following table describes the crcfcs register bit fields. bit field type default value read/ write description 31 status 0 ro detected parity error this bit is set when the bridge detects a parity error, even if parity error handling is disabled (as controlled by bit 6 in the command register). 30 status 0 ro signal system error when set, indicates that the pci-ahb bridge asserted the system error serr_n pin. 29 status 0 ro received master abort when set, indicates that the pci-ahb bridge terminated a master transaction (except for special cycle) with master abort. 28 status 0 ro received target abort when set, indicates that the pci-ahb bridge master transaction was terminated due to a target abort. 27 status 0 ro gener ated target abort when set, indicates that the pci-ahb bridge pci target generated a target abort. 26:25 status 10 ro device select timing these bits encode the timing of devsel#. three allowable timings for assertion of devsel#: 00 ? fast 01 ? medium 10 ? slow 24 status 0 ro data parity report this bit is set when the following three conditions are met: 1) the bus agent asserted perr# itself (on a read) or observed perr# asserted (on a write) 2) the pci-ahb bridge operates as a bus master for the operation that caused the error. 3) the parity error response bit (cfcs[6]) is set. 23:22 reserved 00 reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 20 m9999-031810-1.2 21 status 1 ro 66 mhz capable this read only bit indicates that the pci-ahb bridge is 66 mhz capable. the value is always set to 1. 20 status 1 ro new capability new capabilities are not implemented. 19:10 command 0x0 reserved 9 command 0 ro master fast back-to-back capable master cannot do fast back-to-back transactions to different devices. 8 command 0 ro system error enable enable bit for serr# driver. a value of 0 disables the serr# driver. a value of 1 enables the serr# driver. th is bit?s state after rst# is 0. address parity errors are reported only if this bit and bit 6 are 1. 7 command 0 ro address/data stepping bridge does not do addr ess/data stepping. 6 command 0 ro parity error response when set, the bridge takes its normal action when a parity error is detected. when the bit is 0, the bridge sets its detected parity error status bit (cfcs[31]) when an error is detected, but does not assert perr# and continues normal operation. this bit?s state after rst# is 0. 5 command 0 ro vga palette access vga palette snooping is disabled. 4 command 0 ro memory write and invalidate enable when set, the pci-ahb bridge is allowed to generate the memory write and invalidate command. when reset, the pci-ahb bridge can only generate memory write command. th is bit?s state after rst# is 0. 3 command 0 ro special cycles response bridge ignores all special cycle operations. 2 command 0 ro master operation when set, the pci-ahb bridge is capable of acting as a bus master. when reset, the pci-ahb bridge capability to generate pci accesses is disabled. for normal operat ion, this bit must be set. this bit?s state after rst# is 0. 1 command 0 ro memory space access when set, the pci-ahb bridge res ponds to memory space accesses. when reset, the pci-ahb bridge does not respond to memory space accesses. this bit?s state after rst# is 0. 0 command 0 ro i/o space access when set, the pci-ahb bridge re sponds to i/o space accesses. when reset, the pci-ahb bridge does not respond to i/o space accesses. this bit?s state after rst# is 0.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 21 m9999-031810-1.2 2.3.3 configuration revision register (crcfrv offset pci 0x2008) the crcfrv register contains t he pci-ahb bridge revision number. the following table shows the crcfrv register bit fields. bit field default value read/ write description 31:24 0x06 ro base class indicates device is a bridge, and is equal to 0x06. 23:16 - ro subclass. host/guest mode determined by input pin phgm. 0x00 ? in host bridge mode 0x80 ? in guest bridge mode 15:8 0x00 ro reserved 7:4 0x0 ro revision number indicates the pci-ahb bridge revision number, and is equal to 0h. this number is incremented for subsequent revision. 3:0 0x0 ro step number indicates the pci-ahb bridge step number, and is equal to 0h (chip revision a). this number is incremented for subsequent pci-ahb bridge steps within the current revision. 2.3.4 configuration latency timer register (crcflt pci offset 0x200c) this register configures the cache line size field and the latency timer. the following table shows the crcflt register bit fields. bit field default value read/ write description 31:16 0x0000 ro reserved 15:8 0x00 ro configur ation latency timer specifies, in units of pci bus clocks, t he value of the latency timer of the pci- ahb bridge. when the pci-ahb bridge asserts frame_n, it enables its latency timer to count. if the pci-ah b bridge deasserts frame_n prior to count expiration, the content of the latency timer is ignored. otherwise, after the count expires, the pci-ahb bridge init iates transaction termination as soon as its gnt_n is deasserted. 7:0 0x00 ro cache line size specifies, in unit of 32-bit words(dwor d), the system cache line size. the pci- ahb bridge supports cache line sizes of 4, 8, and 16 dwords. if an attempt is made to write an unsupported value to this register, then writ e is ignored and the pci-ahb bridge does not use the mwi command. if a value other than 8, 16 or 32 is written to the register, the pc i-ahb bridge returns all zeros when the register is read. the driver should use the value of the cache line size to program the cache alignment bits (csr0[15:14]). the pci- ahb bridge uses the cache alignment bits for pci commands that are cache oriented, such as memory-read-line, memory-read-multiple and memory-write-and-invalidate.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 22 m9999-031810-1.2 2.3.5 configuration base memory address (crcbma pci offset 0x2010) the crcbma register specify the base me mory address for accessing the devices on the ahb. this register must be initialized prior to accessing any ahb device with memory access. the following table shows the crcbma register bit fields. bit field default value read/ write description 31:28 - ro configuration base memory address defines the pci memory base address used to access pab and ahb resources. the resources reside in a 64mb address range. the value read depends on cbma. 27:4 0x000000 reserved. 3 0 rw prefetchable 1 ? indicates memory space is prefetchable. 0 ? indicates memory space is not prefetchable. 2:1 00 ro type locate anywhere in 32-bit address space. 0 0 ro memory space indicator determines that the register maps into t he memory space. the value in this field is 0. 2.3.6 configuration base address (pci offsets 0x2014-0x2028) these configuration base addre ss registers are reserved. bit field default value read/ write description 31:0 0x0 reserved. 2.3.7 subsystem id register (crcsid pci offset 0x202c) the crcsid register is a read-only 32-bit register. the c ontent of the crcsid is loaded from the local cpu after a hardware reset. if the crcsid is accessed by the pci host bef ore its content is loaded from the local cpu, the pci-ahb bridge responds with retry termination on the pci bus. the following table shows the crcsid register bit fields. bit field default value read/ write description 31:16 0x0 rw subsystem id indicates a 16-bit field containing the subsystem id. 15:0 0x0 rw subsystem vendor id indicates a 16-bit field containing the subsystem vendor id.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 23 m9999-031810-1.2 the following table shows the a ccess rules of the register. category description value after hardware reset arm9 cpu must program the value for subsystem id and subsystem vendor id during stage 1 power up configuration. write access rules only arm9 cpu can program the subsystem id and subsystem vendor id. this r egister is read-only on the pci bus. 2.3.8 capabilities pointer register (crccap offset 2034h) the ccap register points to the base address of the power management register block in the configuration address space. this pointer is valid only if the new capabilities bit in cfcs is set. the following table shows the crccap register bit fields. read only. bit field default value description 31:8 000000h reserved. 7:0 50 capabilities pointer points to the location of the power management register block in the pci configuration space. the va lue of this field is 50h. 2.3.9 configuration interrupt register (crcfit pci offset 0x203ch) the crcfit register is divided into two sections: the inte rrupt line and the interrupt pin. crcfit configures both the system?s interrupt and the pci-ahb bridge interrupt pin connection. the following table shows the crcfit register bit fields. bit field default value read/ write description 31:24 0x00 ro max_lat this field indicates how often the device needs to gain access to the pci bus. time unit is equal to 0.25 us, assuming a pci cl ock frequency of 33 mhz. the value after a hardware reset is 28h (10 us). 23:16 0x00 ro min_gnt this field indicates the burst period lengt h that the device needs. time unit is equal to 0.25us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 14h (5 us). 15:8 0x01 ro interrupt pin indicates which interrupt pin that the pc i-ahb bridge uses. the pci-ahb bridge uses inta# and the read value is 01h. 7:0 0x00 ro interrupt line provides interrupt line routing information. the basic i/o system (bios) writes the routing information into to this field when it initialized and confi gures the system. the value in this field indicates which one of t he system interrupt controllers is connected to the pci-ahb bridge?s interrupt pin. the driver can use this information to determine priority and vector information. values in this field are system architecture specific.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 24 m9999-031810-1.2 2.3.10 configuration interrupt register (crcfit pci offset 0x203ch) the cfit register is divided into two sections; the interrupt line and the interrupt pin. cfit configures both the system?s interrupt and the pci-ahb brid ge interrupt pin connection. the following table shows the crcfit register bit fields. bit field default value read/ write description 31:24 0x00 ro max_lat this field indicates how often the device needs to gain access to the pci bus. time unit is equal to 0.25 us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 28h (10 us). 23:16 0x00 ro min_gnt this field indicates the burst period length that the device needs. time unit is equal to 0.25us, assuming a pci clock frequency of 33 mhz. the value after a hardware reset is 14h (5 us). 15:8 0x01 ro interrupt pin indicates which interrupt pin that the pc i-ahb bridge uses. the pci-ahb bridge uses inta# and the read value is 01h. 7:0 0x00 r/w interrupt line provides interrupt line routing information. the basic i/o system (bios) writes the routing information into to this field when it initialized and confi gures the system. the value in this field indicates which i of t he system interrupt controller is connected to the pci-ahb bridge?s interrupt pin. the dr iver can use this information to determine priority and vector information. values in this field are system architecture specific. 2.3.11 capabilities id register (crccid offset 2050h) the ccid register is a read-only register that provides information on the ksz8692mpb/KSZ8692XPBp power management capabilities. the following table shows the crccid register bit fields. read only . bit field default value description 31 0 pme support d3(cold) if this bit is set, the ksz8692mpb/KSZ8692XPBp asserts pme in d3(cold) power state. otherwise, the ksz 8692mpb/KSZ8692XPBp does not assert pme in d3(cold). here this bit is set. 30 1 pme support d3(hot) the value of this bit is 1, indicating that the ksz8692mpb/KSZ8692XPBp may assert pme in d3(hot) power state. 29 0 pme support d2 ksz8692mpb/KSZ8692XPBp does not assert pme in d2 state. 28 0 pme support d1 ksz8692mpb/KSZ8692XPBp does not assert pme in d1 state. 27 0 pme support d0 the value of this bit is 0, indi cating that the ksz 8692mpb/KSZ8692XPBp does not assert pme in d0 power state. 26 1 d2 support ksz8692mpb/KSZ8692XPBp support d2 power state. 25 1 d1 support ksz8692mpb/KSZ8692XPBp support d1 power state. 24:22 000 auxiliary current this 3-bit field reports the 3.3vaux auxiliary current requirements for the pci function. if pme# generation from d3_cold is not suppor ted by the function, this field must return a value of 000 when read.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 25 m9999-031810-1.2 21 0 device specific initialization indicates whether special init ialization of this function is required (beyond the standard pci configuration header) befor e the generic class device driver is able to use it. note that this bit is not used by some operating systems. microsoft windows and windows nt, for instance, do not use this bi t to determine whether to use d3. instead the driver?s capabilities is used to determine this. a ?1? indicates that the function require s a device specific initialization sequence following transition to the d0 uninitialization state. 20 0 reserved, should be set to 0. 19 0 pme clock when this bit is a ?1?, it indicates that the function relies on t he presence of the pci clock for pme# operation. when this bit is a ?0?, it indicates that no pci clock is required for the function to generate pme#. 18:16 3h power management pci version(1.2) the value of this bit is 3?b011 15:8 00h next item pointer points to the location of the next bl ock of the capabilities list in the pci configuration space. the value of this fi eld is 00h, indicating that this is the last item of the capability linked list. 7:0 01h capabilities id pci power management registers id. the value of this field is 01h, indicating that this is the power-m anagement register block. 2.3.12 power-management control and status register (crcpmc offset 2054h) the crcpmc register is a read-only register that provides information on the k8842 power management capabilities. the following table shows the crcpmc register bit fields. bit field default value description 31:16 0000h reserved. 15 0(ro, w1c) pme_status this bit indicates that the ksz 8692mpb/KSZ8692XPBp has det ected a power- management event. if bit pme_enable is set, the ksz8692mpb/KSZ8692XPBp also asserts the pme_n pin. this bit is cleared on power-up reset or by write 1. it is not modified by either hardware or software reset. when this bit is cleared, the ksz8692mpb/KSZ8692XPBp deassert s the pme_n pin. 14:9 00h reserved. 8 0(r/w) pme_enable if this bit is set, the ksz8692mpb/ksz 8692xpbp can assert the pme_n pin. otherwise, assertion of the pme_n pin is disabled. this bit is cleared on power-up reset only and is not modified by either hardware or software reset. 7:4 0h reserved.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 26 m9999-031810-1.2 3 1(ro) no soft reset if this bit is set (?1?), the ksz8692mpb/KSZ8692XPBp does not perform an internal reset when transitioning from d3_hot to d0 because of powerstate commands. configuration context is pres erved. upon transition from d3_hot to the d0 initialized state, no additional operating system intervention is required to preserve configurati on context beyond writing the powerstate bits. if this bit is cleared (?0?), the ksz8692mpb/KSZ8692XPBp does perform an internal reset when transitioning from d 3_hot to d0 via software control of the powerstate bits. configuration contex t is lost when performing the soft reset. upon transition from d3_hot to the d0 st ate, a full reinitialization sequence is needed to return the device to d0 initialized. regardless of this bit, devices that transit ion from d3_hot to d0 by a system or bus segment reset will return to the dev ice state d0 uninitialized with only pme context preserved if pm e is supported and enabled. 2 0 reserved. 1:0 00(rw) power state this field is used to set t he current power state of the ksz8692mpb/KSZ8692XPBp and to determine its power state. the definitions of t he field values are: 0: d0 1: d1 2: d2 3: d3(hot) this field gets a value of 0 after power up. 2.3.13 pci-ahb bridge configuration address register (pbca offset 0x2100) the pca register sets the mechanism and address of pci bus c onfiguration cycle. to start a pci configuration cycle, write pca first then read/write p cd to complete the transaction. when initiating a configuration access through pbca and pb cd, the bridge checks the bus number and device number in pbca. if the bus number and device number both equal ?0?, t he bridge assumes that its own configuration register is being accessed and the request will not be forwarded to the pci interface. the bridge will process the configuration access locally. the following table shows the pca register bit fields. bit field default value read/ write description 31 0 wo enable 30:24 0x00 - reserved 23:16 0x00 wo bus number, indicates whether configur ation cycle is on local bus or on another pci bus segment. 15:11 0x00 wo device number, indicates which pci dev ice is accessed using idsel. ad[31:11] are used to connect to idsel. 10:8 0x0 wo function number 7:2 0x00 wo register number, indicates which configuration register is being accessed. 1:0 0x0 wo type translation: 00 ? pci configuration cycle type 00 01 ? pci configuration cycle type 01
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 27 m9999-031810-1.2 31 30 24 23 16 15 11 10 8 7 2 1 0 enable reserved bus number device number function number register number 00 one bit is ?on?, connects to idsel pci device function number register number 00 31 11 10 8 7 2 1 0 31 30 24 23 16 15 11 10 8 7 2 1 0 enable reserved bus number device number function number register number 01 reserved bus number device number function number register number 01 31 24 23 16 15 11 10 8 7 2 1 0 2.3.14 pci-ahb bridge configuration data register (pbcd offset 0x2104) the pcd register provides the data interface for the pci bus configuration cycle. the following table shows the pcd register bit fields. bit field default value read/ write description 31:0 0x00000000 r/w pci configuration register read/write data. read data returned from the pci configuration read cycle. ahb will be re-tri ed until the data is available to be read. write data used in pci conf iguration write cycles. pci configuration header type 00h translation pci configuration header type 01h translation
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 28 m9999-031810-1.2 2.3.15 pci-ahb bridge mode register (pbm offset 0x2200) the pbbm register sets the pci-ahb bridge operating mode. the following table shows the pbbm register bit fields. bit field default value read/ write description 31 1 ro pci-ahb bridge function mode. (read-o nly) selected by power strap option. 1 ? host bridge mode 0 ? guest bridge mode 30:29 00 r/w pci-ahb bridge bus mode 00 : pci mode 01 : mini pci mode 10 : card bus mode 11 : reserved 28:0 0x0 ro reserved 2.3.16 pci-ahb bridge control and status register (pbcs offset 0x2204) the control register contains all the c ontrol bits for the pci-ahb bridge. in host bridge mode, pbcs indicates to the arm when configuration cycles can be generated on the pci bus . in guest bridge mode the pbcs register is read by the pci host to determine when the bridge can be accessed. the following table shows the pbc register bit fields. bit field default value read/ write description 31 0 rw swr software reset when set, the pci-ahb bridge resets all in ternal hardware with the exception of the pci configuration area. 30:29 00 rw prefetch limit allows the user to control the amount of data to be read by a pci-to-ahb burst read. during pci burst read with linear increment mode, the bridge prefetch data from the ahb bus up to the prefetch li mit boundary. during pci burst read with cache line wrap mode, the bri dge prefetch data from the ahb bus up to the smaller value of prefetch limit boundary or t he cacheline size boundary in the pci configuration register. the encoding is as follows: 00 : prefetch limit equals 4 words 01 : prefetch limit equals 8 words 10 : prefetch limit equals 16 words 11 : reserved 28 1 rw pci configuration external access disable 1 : disable pci configuration regist er access on the pci bus. the bridge will respond to pci configuration cycles directed to it with a retry. 0 : the bridge will respond to pci conf iguration cycles directed to it from an external pci device. 28:0 0x0 ro reserved 2.3.17 pci-ahb bridge memory base address register (pmba offset 0x2208) the pmba register defines the ahb address range us ed to generate memory mapped cycles on the pci bus.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 29 m9999-031810-1.2 the following table shows the pmba register bit fields. bit field default value read/ write description 31:12 0x6000_0 rw pci memory mapped base address. for downs tream accesses, this is the start of the ahb address range (range is determined by pmbam) that will generate memory mapped cycles on the pci bus. note the following adress ranges are offlimits: 0x0 ? 0x03ff_ffff 0x4000_0000 ? 0x5fff_ffff 0xc000_0000 ? 0xdfff_ffff 11:0 0x000 ro reserved. 2.3.18 pci-ahb bridge memory base address control register (pmbac offset 0x220c) the pmbac register is used for address translation control. the following table shows the pmbac register bit fields. bit field default value read/ write description 31 0 rw address translation enable if this bit is set, downstream address translation for the memory mapped range is enabled. 30:0 0x0000 ro reserved 2.3.19 pci-ahb bridge memory base address mask (pmbam offset 0x2210) the pmbam register specifies address masking for memory mapped cycles on the pci bus. the following table shows the pmbam register bit fields. bit field default value read/ write description 31:12 0xfc00_0 rw address unmask. for each bit: 1 ? don?t mask the address bit 0 ? mask the address bit note: all the don?t mask bits must be cont iguous. also, this determines the address range (masked address bits) for downstream memory mapped operations. 11:0 0x000 ro because the minimum block size is 4 kb, this field is always 0x000 (the 12 lower address lines are never compared wi th the pmba register value). 2.3.20 pci-ahb bridge memory base address translation (pmbat offset 0x2214) the pmbat register specifies the address translation for pci i/o mapped bus cycles. the following table shows the pmbat register bit fields. bit field default value read/ write description 31:12 - rw translation address this register value is used when addre ss translation is enabled. each value on address lines not masked by pmbam r egister setting is replaced by the corresponding bit value of the pmbat register for pci bus accesses. 11:0 0x000 ro because the minimum block size is 4 kb, this field is always 0x000 (the 12 lower address lines are never compared wi th the pmba register value).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 30 m9999-031810-1.2 2.3.21 pci-ahb bridge i/o base address register (pioba offset 0x2218) the pioba register defines the ahb address range used to generate i/o mapped cycles on the pci bus. the following table shows the pioba register bit fields. bit field default value read/ write description 31:12 0x8000_0 rw pci i/o mapped base address. for downstream accesses, this is the start of the ahb address range (range is determined by piobam) that will generate i/o cycles on the pci bus. note the following adress ranges are offlimits: 0x0 ? 0x03ff_ffff 0x4000_0000 ? 0x5fff_ffff 0xc000_0000 ? 0xdfff_ffff 11:0 0x000 ro reserved. 2.3.22 pci-ahb bridge i/o base address control register (piobac offset 0x221c) the piobac register is used for address translation control. the following table shows the piobac register bit fields. bit field default value read/ write description 31 0 rw address translation enable if this bit is set, downstream address translation for the i/o mapped range is enabled. 30:0 0x0 ro reserved 2.3.23 pci-ahb bridge i/o base address mask (piobam offset 0x2220) the piobam register specifies address masking for pci i/o mapped cycles. the following table shows the piobam register bit fields. bit field default value read/ write description 31:12 0xfc00_0 rw address unmask. for each bit: 1 ? don?t mask the address bit 0 ? mask the address bit note: all the don?t mask bits must be cont iguous. also, this determines the address range (masked address bits) for downstream i/o mapped operations. 11:0 0x000 ro because the minimum block size is 4 kb, this field is always 0x000 (the 12 lower address lines are never compared with the piobam register value). 2.3.24 pci-ahb bridge i/o base address translation (piobat offset 0x2224) the piobat register specifies the addre ss translation for pci i/o mapped bus cycles. the following table shows the piobat register bit fields. bit field default value read/ write description 31:12 - rw translation address this register value is used when addre ss translation is enabled. each value on address lines not masked by piobam r egister setting is replaced by the corresponding bit value of the piobat register for pci bus accesses. 11:0 0x000 ro because the minimum block size is 4 kb, this field is always 0x000 (the 12 lower address lines are never compared with the piobat register value).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 31 m9999-031810-1.2 2.4 ddr memory controller register (0x4000-0x4fff) a register may contain multiple parameters, a single parameter, or partial data for a parameter. as a result, a read of or a write to a particular parameter may require multiple r ead or write commands to different register addresses. while parameters can be of any size, each parameter is mapped to byte boundaries that will fit the entire parameter. unused bits are considered reserved and indicated with a resv tag. reserved fields will return 0 on all register reads. parameter size (in bits) mapping size starting address 1 to 8 1 byte byte boundary 9 to 16 2 bytes 2 byte boundary 17 to 128 4 bytes 4 byte boundary parameter size to mapping condition name ahb register address access parameter(s) ddr_ctl_00 0x00 rw rw rw rw bank_split_en addr_cmp_en command_age_count age_count ddr_ctl_01 0x04 rw rw rw rw fast_write rw_same_en priority_en placement_en ddr_ctl_02 0x08 rd rw rw rw int_status dll_increment dll_start_point q_fullness ddr_ctl_03 0x0c rw rd rw wr ahb0_r_priority out_of_range_type int_mask int_ack ddr_ctl_04 0x10 rd rw rw rw ahb0_current_bdw ahb0_bdw_ovflow ahb0_bdw ahb0_w_priority ddr_ctl_05 0x14 rw rw rw rw ahb1_bdw_ovflow ahb1_bdw ahb1_w_priority ahb1_r_priority ddr_ctl_06 0x18 rw rw rw rd ahb2_bdw ahb2_w_priority ahb2_r_priority ahb1_current_bdw ddr_ctl_07 0x1c rw rw rd rw ahb3_w_priority ahb3_r_priority ahb2_current_bdw ahb2_bdw_ovflow ddr_ctl_08 0x20 rw rd rw rw ahb4_r_priority ahb3_current_bdw ahb3_bdw_ovflow ahb3_bdw ddr_ctl_09 0x24 rd rw rw rw ahb4_current_bdw ahb4_bdw_ovflow ahb4_bdw ahb4_w_priority
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 32 m9999-031810-1.2 ddr_ctl_10 0x28 rw rw rw rw ahb5_bdw_ovflow ahb5_bdw ahb5_w_priority ahb5_r_priority ddr_ctl_11 0x2c rw rw rw rd ahb6_bdw ahb6_w_priority ahb6_r_priority ahb5_current_bdw ddr_ctl_12 0x30 rw rw rd rw ahb7_w_priority ahb7_r_priority ahb6_current_bdw ahb6_bdw_ovflow ddr_ctl_13 0x34 rw rd rw rw arb_cmd_q_threshold ahb7_current_bdw ahb7_bdw_ovflow ahb7_bdw ddr_ctl_14 0x38 rd rd rd rw max_cs_reg max_col_reg max_row_reg start ddr_ctl_15 0x3c rw rw rw rw caslat caslat_lin_gate caslat_lin initaref ddr_ctl_16 0x40 rw rw rw rw trc tpdex trrd bstlen ddr_ctl_17 0x44 rw rw rw rw tmrd temrs trp tras_min ddr_ctl_18 0x48 rw rw rw writeinterp twtr trfc ddr_ctl_19 0x4c rw wr rw wr_dqs_shift arefresh auto_refresh_mode ddr_ctl_20 0x50 wr rw rw rw write_modereg cs_map no_cmd_init wr_dqs_shift_bypass ddr_ctl_21 0x54 rw+ rw srefresh power_down ddr_ctl_22 0x58 rw rw rw rw concurrentap ap drive_dq_dqs tcke ddr_ctl_23 0x5c rw rw rw rw tras_lockout intrptapburst intrptwritea intrptreada ddr_ctl_24 0x60 rw rw rw rw dll_bypass_mode tdal twr_int trcd_int
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 33 m9999-031810-1.2 ddr_ctl_25 0x64 rd rw rw rw dll_lock aprebit column_size addr_pins ddr_ctl_26 0x68 rw rw rw rw dll_dqs_delay_3 dll_dqs_delay_2 dll_dqs_delay_1 dll_dqs_delay_0 ddr_ctl_27 0x6c rw rw rw rw dll_dqs_delay_bypass_3 dll_dqs_delay_bypass_2 dll_dqs_delay_bypass_1 dll_dqs_delay_bypass_0 ddr_ctl_28 0x70 rd rw rw out_of_range_length dqs_out_shift_bypass dqs_out_shift ddr_ctl_29 0x74 rw rw ahb0_rdcnt ahb0_wrcnt ddr_ctl_30 0x78 rw rw ahb1_rdcnt ahb1_wrcnt ddr_ctl_31 0x7c rw rw ahb2_rdcnt ahb2_wrcnt ddr_ctl_32 0x80 rw rw ahb3_rdcnt ahb3_wrcnt ddr_ctl_33 0x84 rw rw ahb4_rdcnt ahb4_wrcnt ddr_ctl_34 0x88 rw rw ahb5_rdcnt ahb5_wrcnt ddr_ctl_35 0x8c rw rw ahb6_rdcnt ahb6_wrcnt ddr_ctl_36 0x90 rw rw ahb7_rdcnt ahb7_wrcnt ddr_ctl_37 0x94 rw rd tref version ddr_ctl_38 0x98 rw tras_max ddr_ctl_39 0x9c rw emrs_data ddr_ctl_40 0xa0 rd out_of_range_addr ddr_ctl_41 0xa4 rd rw rw rd out_of_range_source_id reg_dimm_enable reduc dlllockreg ddr_ctl_42 0xa8 rw rd tdll port_busy ddr_ctl_43 0xac rw rw txsr txsnr ddr_ctl_44 0xb0 rw tinit note: access refers to the writeability of the parameter. rw = read/write. rd = read only. wr = write only. rw+ = read/write, where one or more bits of the paramet er have additional functionality and require special handling.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 34 m9999-031810-1.2 2.4.1 ddr_ctl_00 register parameters (ddr offset 0x00) bit field default value read/ write description 31:25 - - reserved 24 0 rw bank_split_en enable bank splitting for cmd queue placement logic. 23:15 - - reserved 16 0 rw addr_cmp_en enable address collision detection for cmd queue placement logic. 15:11 - - reserved 10:8 0 rw command_age_count initial value of individual cm d aging counters for cmd aging. 7:3 - - reserved 2:0 0 rw age_count initial value of master aging -rate counter for cmd aging. 2.4.2 ddr_ctl_01 register parameters (ddr offset 0x04) bit field default value read/ write description 31:25 - - reserved 24 0 rw fast_write sets when write cmds are issued to dram devices. 23:15 - - reserved 16 0 rw rw_same_en enable read/write grouping for cmd queue placement logic. 15:9 - - reserved 8 0 rw priority_en enable priority for cmd queue placement logic. 7:1 - - reserved 0 0 rw placement_en enable placement logic for cmd queue.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 35 m9999-031810-1.2 2.4.3 ddr_ctl_02 register parameters (ddr offset 0x08) bit field default value read/ write description 31:30 - - reserved 29:24 0 ro int_status status of interrupt features in the controller. read-only 23 - - reserved 22:16 0 rw dll_increment number of elements to add to dll_start_point when searching for lock. 15 - - reserved 14:8 0 rw dll_start_point initial delay count when searching for lock in master dll. 7:2 - - reserved 1:0 0 rw q_fullness quantity that dete rmines cmd queue full. 2.4.4 ddr_ctl_03 register parameters (ddr offset 0x0c) bit field default value read/ write description 31:27 - - reserved 26:24 0 rw ahb0_r_priority priority of read cmds from port 0. 23:18 - - reserved 17:16 0 ro out_of_range_type type of cmd that caused an out-of-range interrupt 15:14 - - reserved 13:8 0 rw int_mask mask for controller_int signals from the int_status parameter. 7:5 - - reserved 4:0 0 wo int_ack clear mask of the int_status parameter.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 36 m9999-031810-1.2 2.4.5 ddr_ctl_04 register parameters (ddr offset 0x10) bit field default value read/ write description 31 - - reserved 30:24 0 ro ahb0_current_bdw current bandwidth usage percentage for port 0. 23:17 - - reserved 16 0 rw ahb0_bdw_ovflow port 0 behavior when bandwidth maximized. 15 - - reserved 14:8 0 rw ahb0_bdw maximum bandwidth percentage for port 0. 7:3 - - reserved 2:0 0 rw ahb0_w_priority priority of write cmds from port 0. 2.4.6 ddr_ctl_05 register parameters (ddr offset 0x14) bit field default value read/ write description 31:25 - - reserved 24 0 rw ahb1_bdw_ovflow port 1 behavior when bandwidth maximized. 23 - - reserved 22:16 0 rw ahb1_bdw maximum bandwidth percentage for port 1. 15:11 - - reserved 10:8 0 rw ahb1_w_priority priority of write cmds from port 1. 7:3 - - reserved 2:0 0 rw ahb1_r_priority priority of read cmds from port 1.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 37 m9999-031810-1.2 2.4.7 ddr_ctl_06 register parameters (ddr offset 0x18) bit field default value read/ write description 31 - - reserved 30:24 0 rw ahb2_bdw maximum bandwidth percentage for port 2. 23:19 - - reserved 18:16 0 rw ahb2_w_priority priority of write cmds from port 2. 15:11 - - reserved 10:8 0 rw ahb2_r_priority priority of read cmds from port 2. 7 - - reserved 6:0 0 ro ahb1_current_bdw current bandwidth usage percentage for port 1. 2.4.8 ddr_ctl_07 register parameters (ddr offset 0x1c) bit field default value read/ write description 31:27 - - reserved 26:24 0 rw ahb3_w_priority priority of write cmds from port 3. 23:19 - - reserved 18:16 0 rw ahb3_r_priority priority of read cmds from port 3. 15 - - reserved 14:8 0 ro ahb2_current_bdw current bandwidth usage percentage for port 2. 7:1 - - reserved 0 0 ro ahb2_bdw_ovflow port 2 behavior when bandwidth maximized.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 38 m9999-031810-1.2 2.4.9 ddr_ctl_08 register parameters (ddr offset 0x20 bit field default value read/ write description 31:27 - - reserved 26:24 0 rw ahb4_r_priority priority of read cmds from port 4. 23 - - reserved 22:16 0 ro ahb3_current_bdw current bandwidth usage percentage for port 3. 15:9 - - reserved 8 0 ro ahb3_bdw_ovflow port 3 behavior when bandwidth maximized. 7 - - reserved 6:0 0 rw ahb3_bdw maximum bandwidth percentage for port 3. 2.4.10 ddr_ctl_09 register parameters (ddr offset 0x24) bit field default value read/ write description 31 - - reserved 30:24 0 ro ahb4_ current_bdw current bandwidth usage percentage for port 4. 23:17 - - reserved 16 0 rw ahb4_bdw_ovflow port 4 behavior when bandwidth maximized. 15 - - reserved 14:8 0 rw ahb4_bdw maximum bandwidth percentage for port 4. 7:3 - - reserved 2:0 0 rw ahb4_w_priority priority of write cmds from port 4.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 39 m9999-031810-1.2 2.4.11 ddr_ctl_10 register parameters (ddr offset 0x28) bit field default value read/ write description 31:25 - - reserved 24 0 rw ahb5_bdw_ovflow port 5 behavior when bandwidth maximized. 23 - - reserved 22:16 0 rw ahb5_bdw maximum bandwidth percentage for port 5. 15:11 - - reserved 10:8 0 rw ahb5_w_priority priority of write cmds from port 5. 7:3 - - reserved 2:0 0 rw ahb5_r_priority priority of read cmds from port 5. 2.4.12 ddr_ctl_11 register parameters (ddr offset 0x2c) bit field default value read/ write description 31 - - reserved 30:24 0 rw ahb6_bdw maximum bandwidth percentage for port 6. 23:19 - - reserved 18:16 0 rw ahb6_w_priority priority of write cmds from port 6. 15:11 - - reserved 10:8 0 rw ahb6_r_priority priority of read cmds from port 6. 7 - - reserved 6:0 0 ro ahb5_current_bdw current bandwidth usage percentage for port 5.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 40 m9999-031810-1.2 2.4.13 ddr_ctl_12 register parameters (ddr offset 0x30) bit field default value read/ write description 31:27 - - reserved 26:24 0 rw ahb7_w_priority priority of write cmds from port 7. 23:19 - - reserved 18:16 0 rw ahb7_r_priority priority of read cmds from port 7. 15 - - reserved 14:8 0 ro ahb6_current_bdw current bandwidth usage percentage for port 6. 7:1 - - reserved 0 0 ro ahb6_bdw_ovflow port 6 behavior when bandwidth maximized. 2.4.14 ddr_ctl_13 register parameters (ddr offset 0x34) bit field default value read/ write description 31:26 - - reserved 25:24 0 rw arb_cmd_q_threshold threshold for cmd queue fullness related to overflow. 23 - - reserved 22:16 0 ro ahb7_current_bdw current bandwidth usage percentage for port 7. 15:9 - - reserved 8 0 ro ahb7_bdw_ovflow port 7 behavior when bandwidth maximized. 7 - - reserved 6:0 0 rw ahb7_bdw maximum bandwidth percentage for port 7.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 41 m9999-031810-1.2 2.4.15 ddr_ctl_14 register parameters (ddr offset 0x38) bit field default value read/ write description 31:26 - - reserved 25:24 0 ro max_cs_reg maximum number of chip selects available. default = 0x2 23:20 - - reserved 19:16 0 ro max_col_reg maximum width of column address in drams. default = 0xc 15:12 - - reserved 11:8 0 ro max_row_reg maximum width of memory address bus. default = 0xe 7:1 - - reserved 0 0 rw start initiate cmd processing in the controller. 2.4.16 ddr_ctl_15 register parameters (ddr offset 0x3c) bit field default value read/ write description 31:27 - - reserved 26:24 0 rw caslat encoded cas latency sent to drams during initialization. 23:21 - - reserved 20:16 0 rw caslat_lin_gate adjusts data capture gate open by half cycles. 15:11 - - reserved 12:8 0 rw caslat_lin sets latency from read cmd send to data receive from/to controller. 7:4 - - reserved 3:0 0 rw initaref number of auto-refresh cmds to execute during dram initialization.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 42 m9999-031810-1.2 2.4.17 ddr_ctl_16 register parameters (ddr offset 0x40) bit field default value read/ write description 31:29 - - reserved 28:24 0 rw trc dram trc parameter in cycles. 23:19 - - reserved 18:16 0 rw tpdex dram tpdex parameter in cycles. 15:11 - - reserved 10:8 0 rw trrd dram trrd parameter in cycles. 7:3 - - reserved 2:0 0 rw bstlen encoded burst length sent to drams during initialization. 2.4.18 ddr_ctl_17 register parameters (ddr offset 0x44) bit field default value read/ write description 31:29 - - reserved 28:24 0 rw tmrd dram tmrd parameter in cycles. 23:18 - - reserved 17:16 0 rw temrs dram temrs parameter in cycles. 15:12 - - reserved 11:8 0 rw trp dram trp parameter in cycles. 7:0 0 rw tras_min dram tras_min parameter in cycles. 2.4.19 ddr_ctl_18 register parameters (ddr offset 0x48) bit field default value read/ write description 31:25 - - reserved 24 0 rw writeinterp allow controller to interrupt a write burst to the drams with a read cmd. 23:19 - - reserved 18:16 0 rw twtr dram twtr parameter in cycles. 15:8 - - reserved 7:0 0 rw trfc dram trfc parameter in cycles.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 43 m9999-031810-1.2 2.4.20 ddr_ctl_19 register parameters (ddr offset 0x4c) bit field default value read/ write description 31 - - reserved 30:24 0 rw wr_dqs_shift fraction of a cycle to delay the clk_wr signal in the controller. 23:17 - - reserved 16 0 wo arefresh initiate auto-refresh when specified by auto_refresh_mode 15:7 - - reserved 8 0 rw auto_refresh_mode sets if auto-refresh will be at next burst or next cmd boundary. 7:0 - - reserved 2.4.21 ddr_ctl_20 register parameters (ddr offset 0x50) bit field default value read/ write description 31:25 - - reserved 24 0 wo write_modereg write emrs data to the drams 23:18 - - reserved 17:16 0 rw cs_map number of active chip selects used in address decoding. 15:9 - - reserved 8 0 rw no_cmd_init disable dram cmds until tdll has ex pired during initialization. 7 - - reserved 6:0 0 rw wr_dqs_shift_bypass fraction of a cycle to delay the clk_wr signal in the controller when bypassed. 2.4.22 ddr_ctl_21 register parameters (ddr offset 0x54) bit field default value read/ write description 31:25 - - reserved 24 0 rw srefresh place drams in self-refresh mode. 23:1 - - reserved 0 0 rw power_down disable clock enable and set drams in power-down state.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 44 m9999-031810-1.2 2.4.23 ddr_ctl_22 register parameters (ddr offset 0x58) bit field default value read/ write description 31:25 - - reserved 24 0 rw concurrentap allow controller to issue cmds to other banks while a bank is in auto pre-charge. 23:17 - - reserved 16 0 rw ap enable auto pre-charge mode of controller. 15:9 - - reserved 8 0 rw drive_dq_dqs set dq/dqs output enable behavior when controller is idle. 7:3 - - reserved 2:0 0 rw tcke minimum cke pulse width. 2.4.24 ddr_ctl_23 register parameters (ddr offset 0x5c) bit field default value read/ write description 31:25 - - reserved 24 0 rw tras_lockout allow the controller to execute auto pr e-charge cmds before tras_min expires. 23:17 - - reserved 16 0 rw intrptapburst allow the controller to interrupt an auto pre-charge cmd with another cmd. 15:9 - - reserved 8 0 rw intrptwritea allow the controller to interrupt a comb ined write with auto pre-charge cmd with another write cmd. 7:1 - - reserved 0 0 rw intrptreada allow the controller to interrupt a comb ined read with auto pre-charge cmd with another read cmd.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 45 m9999-031810-1.2 2.4.25 ddr_ctl_24 register parameters (ddr offset 0x60) bit field default value read/ write description 31:25 - - reserved 24 0 rw dll_bypass_mode enable the dll bypass feat ure of the controller. 23:20 - - reserved 19:16 0 rw tdal dram tdal parameter in cycles. 15:11 - - reserved 10:8 0 rw twr_int dram twr_int parameter in cycles. 7:0 0 rw trcd_int dram trcd_int parameter in cycles. 2.4.26 ddr_ctl_25 register parameters (ddr offset 0x64) bit field default value read/ write description 31 - - reserved 30:24 0 ro dll_lock number of delay elements in master dll lock. 23:20 - - reserved 19:16 0 rw aprebit location of the aut o pre-charge bit in the dram address. 15:11 - - reserved 10:8 0 rw column_size difference between number of column pins available and number being used. 7:3 - - reserved 2:0 0 rw addr_pins difference between number of addr pins available and number being used.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 46 m9999-031810-1.2 2.4.27 ddr_ctl_26 register parameters (ddr offset 0x68) bit field default value read/ write description 31 - - reserved 30:24 0 rw dll_dqs_delay_3 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 3 during reads. 23 - - reserved 22:16 0 rw dll_dqs_delay_2 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 2 during reads. 15 - - reserved 14:8 0 rw dll_dqs_delay_1 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 1 during reads. 7 - - reserved 6:0 0 rw dll_dqs_delay_0 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 0 during reads. 2.4.28 ddr_ctl_27 register parameters (ddr offset 0x6c) bit field default value read/ write description 31 - - reserved 30:24 0 rw dll_dqs_delay_bypass_3 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 3 during reads when dll is being bypassed. 23 - - reserved 22:16 0 rw dll_dqs_delay_bypass_2 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 2 during reads when dll is being bypassed. 15 - - reserved 14:8 0 rw dll_dqs_delay_bypass_2 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 1 during reads when dll is being bypassed. 7 - - reserved 6:0 0 rw dll_dqs_delay_bypass_0 fraction of a cycle to delay the dqs signal from the dram for dll_rd_dqs_slice 0 during reads when dll is being bypassed.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 47 m9999-031810-1.2 2.4.29 ddr_ctl_28 register parameters (ddr offset 0x70) bit field default value read/ write description 31:26 - - reserved 25:16 0 ro out_of_range_length length of cmd that caused an out-of-range interrupt. 15 - - reserved 14:8 0 rw dqs_out_shift_bypass fraction of a cycle to delay the write dqs signal to the drams during writes when the dll is being bypassed. 7 - - reserved 6:0 0 rw dqs_out_shift fraction of a cycle to delay the dqs signal to the dram during writes. 2.4.30 ddr_ctl_29 register parameters (ddr offset 0x74) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb0_rdcnt number of bytes for an incr read cmd on port 0. 15:11 - - reserved 10:0 0 rw ahb0_wrcnt number of bytes for an incr write cmd on port 0. 2.4.31 ddr_ctl_30 register parameters (ddr offset 0x78) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb1_rdcnt number of bytes for an incr read cmd on port 1. 15:11 - - reserved 10:0 0 rw ahb1_wrcnt number of bytes for an incr write cmd on port 1. 2.4.32 ddr_ctl_31 register parameters (ddr offset 0x7c) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb2_rdcnt number of bytes for an incr read cmd on port 2. 15:11 - - reserved 10:0 0 rw ahb2_wrcnt number of bytes for an incr write cmd on port 2.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 48 m9999-031810-1.2 2.4.33 ddr_ctl_32 register parameters (ddr offset 0x80) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb3_rdcnt number of bytes for an incr read cmd on port 3. 15:11 - - reserved 10:0 0 rw ahb3_wrcnt number of bytes for an incr write cmd on port 3. 2.4.34 ddr_ctl_32 register parameters (ddr offset 0x84) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb4_rdcnt number of bytes for an incr read cmd on port 4. 15:11 - - reserved 10:0 0 rw ahb4_wrcnt number of bytes for an incr write cmd on port 4. 2.4.35 ddr_ctl_33 register parameters (ddr offset 0x88) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb5_rdcnt number of bytes for an incr read cmd on port 5. 15:11 - - reserved 10:0 0 rw ahb5_wrcnt number of bytes for an incr write cmd on port 5. 2.4.36 ddr_ctl_34 register parameters (ddr offset 0x8c) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb6_rdcnt number of bytes for an incr read cmd on port 6. 15:11 - - reserved 10:0 0 rw ahb6_wrcnt number of bytes for an incr write cmd on port 6.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 49 m9999-031810-1.2 2.4.37 ddr_ctl_35 register parameters (ddr offset 0x8c) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb6_rdcnt number of bytes for an incr read cmd on port 6. 15:11 - - reserved 10:0 0 rw ahb6_wrcnt number of bytes for an incr write cmd on port 6. 2.4.38 ddr_ctl_36 register parameters (ddr offset 0x90) bit field default value read/ write description 31:27 - - reserved 26:16 0 rw ahb7_rdcnt number of bytes for an incr read cmd on port 7. 15:11 - - reserved 10:0 0 rw ahb7_wrcnt number of bytes for an incr write cmd on port 7. 2.4.39 ddr_ctl_37 register parameters (ddr offset 0x94) bit field default value read/ write description 31:28 - - reserved 27:16 0 rw tref dram tref parameter in cycles. 15:0 0 ro version controller version number default = 0x2042 2.4.40 ddr_ctl_38 register parameters (ddr offset 0x98) bit field default value read/ write description 31:16 - - reserved 15:0 0 rw tras_max dram tras_max parameter in cycles. 2.4.41 ddr_ctl_39 register parameters (ddr offset 0x9c) bit field default value read/ write description 31:14 - - reserved 13:0 0 rw emrs_data extended mode register data writt en during initialization or when write_modereg set.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 50 m9999-031810-1.2 2.4.42 ddr_ctl_40 register parameters (ddr offset 0xa0) bit field default value read/ write description 31 - - reserved 30:0 0 ro out_of_range_addr address of cmd that caus ed an out-of-range interrupt. 2.4.43 ddr_ctl_41 register parameters (ddr offset 0xa4) bit field default value read/ write description 31:27 - - reserved 26:24 0 ro out_of_range_source_id source id of cmd that caused an out-of-range interrupt. 23:17 - - reserved 16 0 rw reg_dimm_enable enable registered dimm operat ion of the controller. 15:9 - - reserved 8 0 rw reduc enable the half datapath feat ure of the controller. 7:1 - - reserved 0 0 ro dlllockreg status of dll lock coming out of master delay. 2.4.44 ddr_ctl_42 register parameters (ddr offset 0xa8) bit field default value read/ write description 31:24 - - reserved 23:8 0 rw tdll dram tdll parameter in cycles. 7:0 0 ro port_busy per-port indicator that the cont roller is processing a cmd. 2.4.45 ddr_ctl_43 register parameters (ddr offset 0xac) bit field default value read/ write description 31:16 0 rw txsr dram txsr parameter in cycles. 15:0 0 rw txsnr dram txsnr parameter in cycles. 2.4.46 ddr_ctl_44 register parameters (ddr offset 0xb0) bit field default value read/ write description 31:24 - - reserved 23:0 0 rw tinit dram tinit parameter in cycles.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 51 m9999-031810-1.2 2.4.47 ddr_ctl parameter descriptions parameter description addr_cmp_en [0] e nables address collision/data coherency det ection as a condition when using the placement logic to fill the command queue. 'b0 = disabled 'b1 = enabled addr_pins [2:0] defines the difference betw een the maximum number of addre ss pins configured (14) and the actual number of pi ns being used. the user address is aut omatically shifted so that the user address space is mapped contiguously into the memory map based on the value of this parameter. age_count [2:0] holds the initial value of the master aging-rate c ounter. when using the pl acement logic to fill the command queue, the command aging counters will be decre mented one each time the master aging-rate counter counts down age_count cycles. ahbx_bdw [6:0] sets the maximum bandwidth allocation percentage for ahb port x. the percentage must be specified as a hex value (0x01 - 0x64) r epresenting a decimal per centage value from 1 - 100. ahbx_bdw_ovflow [0] determines the behavior of ahb port x when the ma ximum bandwidth has been reached. 'b0 = the port does not have access to the me mory controller when its bandwidth allocation has been exceeded, even if the memory controller can accept the command. 'b1 = the port may exceed the bandwidth allo cation if the command queue is less than half full and no other requestors (with ava ilable bandwidth) are requesting access. ahbx_current_bdw [6:0] holds the current bandwidth usage of ahb port x as ca lculated by the arbiter. the percentage will be specified as a hex value (0 x01 - 0x64) representing a decimal percentage value from 1 - 100. this parameter is read-only. ahbx_r_priority [2:0] sets the priority of r ead commands from ahb port x. a value of 0 is the highest priority. ahbx_rdcnt [10:0] holds the number of bytes to return to ahb port x for an i ncr read ahb command. the ahb logic will subdivide a request into bursts of the size of this parameter. a value of 0 indicates that 2 n+1 words will be returned. the logic w ill continue requesting bursts of this size as soon as the previous request has been received by the ahb port. if the incr command is terminated on an unnatural boundary, the logic will discard the unnecessary words. ahbx_w_priority [2:0] sets the priority of write commands from ahb port x. a value of 0 is the highest priority. ahbx_wrcnt [10:0] holds the number of bytes to s end to the memory controller from ahb port x for an incr write ahb command. the ahb logic will subdivide the request into burst s of the size of this parameter. a value of 0 indicates that 2 n+1 words will be sent in one burst. the logic will continue sending bursts of this size as soon as the previous request has been transmitted by the ahb port. if the incr command is terminat ed on an unnatural boundary, the logic will mask out the unnecessary words. ap [0] enables auto pre-charge mode for dram devices. note: this parameter may not be modified a fter the start parameter has been asserted. 'b0 = auto pre-charge mode disabled. me mory banks will stay open until another request requires this bank, the maximum open time (tra s_max) has elapsed, or a refresh command closes all the banks. 'b1 = auto pre-charge mode enabled. all read and write transactions must be terminated by an auto pre-charge command. if a tr ansaction consists of multiple read or write bursts, only the last command is issued with an auto pre-charge. aprebit [3:0] defines the location of the auto pre- charge bit in the dram address in decimal encoding. arb_cmd_q_threshold [1:0] sets the comm and queue fullness that determines if ports will be allowed to overflow. this parameter is used in conjunction with the ahbx_bdw_ovflow parameters.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 52 m9999-031810-1.2 arefresh [0] initiates an automatic refresh to the dram devices based on the setting of the auto_refresh_mode parameter. if there are any open banks when th is parameter is set, the databahn memory controller will automatically close these banks before issuing the auto- refresh command. this parameter will always read back "0". 'b0 = no action 'b1 = issue refresh to the dram devices auto_refresh_mode [0] sets the m ode for when the automatic refresh will occur. if auto_refresh_mode is set and a refresh is required to memory, the memory c ontroller will delay this refresh until the end of the current transaction (if the transaction is fully contained inside a single page), or until the current transaction hits t he end of the current page. 'b0 = issue refresh on the next dram burst boundary, even if the cu rrent command is not complete. 'b1 = issue refresh on the next command boundary. bank_split_en [0] e nables bank splitting as a condition when usi ng the placement logi c to fill the command queue. 'b0 = disabled 'b1 = enabled bstlen [2:0] defines the burst length encoding that will be progra mmed into the dram devices at initialization. 'b001 = 2 words (this setting is reserved when the reduc parameter is set to 1 for half datapath mode.) 'b010 = 4 words 'b011 = 8 words all other settings are reserved caslat [2:0] sets the cas (column address strobe) latency encoding that the memory uses. the binary value programmed into this parameter is dependent on the memory device, since the same caslat value may have different meanings to different memories. this will be programmed into the dram devices at in itialization. the cas encoding will be specified in the dram spec sheet, and should correspond to the caslat_lin parameter. caslat_lin [4:0] sets the cas latency linear value in 1/ 2 cycle increments. this se ts an internal adjustment for the delay from when the read command is s ent from the memory controller to when data will be received back. the window of time in whic h the data is captured is a fixed length. the caslat_lin parameter adjusts the st art of this data capture window. note: not all linear values will be supported fo r the memory devices being used. refer to the specification for the me mory devices being used. 'b00000 - 'b00010 = reserved 'b00011 = 1.5 cycles 'b00100 = 2 cycles 'b00101 = 2.5 cycles 'b00110 = 3 cycles 'b00111 = 3.5 cycles 'b01000 = 4 cycles 'b01001 = reserved 'b01010 = 5 cycles all other settings reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 53 m9999-031810-1.2 caslat_lin_gate [4:0] adjusts the data capture gate open time by 1/2 cycle increm ents. this parameter is programmed differently than caslat _lin when there are fixed offs ets in the fli ght path between the memories and the memory controller for cl ock gating. when caslat _lin_gate is a larger value than caslat_lin, the data capture window will become shor ter. a caslat_lin_gate value smaller than caslat_lin may have no effect on the data captur e window, depending on the fixed offsets in t he asic and the board. 'b00000 - 'b00010 = reserved 'b00011 = 1.5 cycles 'b00100 = 2 cycles 'b00101 = 2.5 cycles 'b00110 = 3 cycles 'b00111 = 3.5 cycles 'b01000 = 4 cycles 'b01001 = reserved 'b01010 = 5 cycles all other settings reserved column_size [2:0] shows the difference between the ma ximum column width avail able (12) and the actual number of column pins being us ed. the user address is automat ically shifted so that the user address space is mapped contiguously into the memory map based on the value of this parameter. command_age_count [2:0] holds the initial value of the comm and aging counters associated with each command in the command queue. when using the placement logi c to fill the command queue, the command aging counters decrement one eac h time the master aging-rate counter counts down age_count cycles. concurrentap [0] enables concurr ent auto pre-charge. some dram dev ices do not allow one bank to be auto pre-charged while another bank is reading or writing. the jedec standard allows concurrent auto pre-charge. set this parameter for the dram device being used. 'b0 = concurrent auto pre-charge disabled. 'b1 = concurrent aut o pre-charge enabled. cs_map [1:0] sets the mask that determines which chip select pins are active. the user address chip select field will be mapped into the active chip selects indicated by this parameter in ascending order from lowest to highest. this allows the memory controller to map the entire contiguous user address into any group of chip selects. bit 0 of this parameter corresponds to chip select [0]. note that the number of chip selects, the number of bits set to 1 in this parameter, must be a power of 2 (2 0 , 2 1 , 2 2 , etc.) dll_bypass_mode [0] defines the behavior of the dll bypass logic and estab lishes which set of delay parameters will be used. when dll_bypass_mode is set to 0, the va lues programmed in the dll_dqs_delay_x, dqs_out_shift, and wr_dqs_shift are used. these parameters add fractional increments of the clock to the specified lines. when dll_bypass_mode is set to 1, the values programmed into the dll_dqs_delay_bypass_x, dqs_out_shift_bypass, and wr_dqs_shift_bypass are used. these parameters specify the actual number of delay elements added to each of the lines. if the total delay time programmed into the delay parameters exceeds the number of delay elements in the delay chain, then the delay will be set to the maximum number of delay elements in the delay chain. 'b0 = normal operational mode. 'b1 = bypass the dll master delay line.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 54 m9999-031810-1.2 dll_dqs_delay_x [6:0] sets the delay for the r ead_dqs signal from the ddr sdram devices for dll_rd_dqs_slice x. this delay is used center the edges of the read_dqs signal so that the read data will be captured in the middle of the valid window in the i/o logic. each increment of this param eter adds a delay of 1/128 of the system clock. the same delay will be added to the read_dqs signal for each byte of the read data. dll_dqs_delay_bypass_x [6:0] sets the delay for the r ead_dqs signal from the ddr sdram devices for dll_rd_dqs_slice x for reads when the dll is being bypassed. th is delay is used cent er the edges of the read_dqs signal so that the read data will be captured in the middle of the valid window in the i/o logic. the value programmed into this parameter sets the actual number of delay elements in the read_dqs line. the same delay will be added to t he read_dqs signal for each byte of the read data. if the total delay time programmed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. dll_increment [6:0] defines the number of delay elements to recursively increment t he dll_start_poi nt parameter with when searching for lock. dll_lock [6:0] defines the actual number of delay elements used to capture one full clock cycle. this parameter is automatic ally updated every time a refres h operation is performed. this parameter is read-only. dll_start_point [6:0] sets the number of delay elements to place in the master delay line to start searching for lock in master dll. dlllockreg [0] dll lock/unlock. this parameter is r ead-only. dqs_out_shift [6:0] sets the delay for the clk _dqs_out signal of the dll_wr_dqs _slice to ensure correct data capture in the i/o logic. each increment of this parameter adds a delay of 1/128 of the system clock. dqs_out_shift_bypass [6:0] sets the delay for the clk _dqs_out signal of the dll_wr_dqs_s lice when the dll is being bypassed. this is used to ensure corre ct data capture in the i/o logic. the value programmed into this parameter sets the actual number of delay elements in the clk_dqs_out line. if the total delay time progr ammed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. drive_dq_dqs [0] selects if the dq output enables and dqs output enables w ill be driven active when the memory controller is in an idle state. 'b0 = leave the output enables de-asserted when idle. 'b1 = drive the output enables active when idle. emrs_data [13:0] holds the emrs data written during ddrii initialization. the cont ents of this parameter will be programmed into the dram at initializat ion or when the writ e_modereg parameter is written with a "1". consult the dram specificat ion for the correct settings for this parameter. fast_write [0] controls when the write commands are issued to the dram devices. 'b0 = the memory controller will issue a wr ite command to the dram devices when it has received enough data for one dram burst. in this m ode, write data can be sent in any cycle relative to the write command. this mode also allows for multi-word write command data to arrive in non-sequential cycles. 'b1 = the memory controller will issue a writ e command to the dram devices after the first word of the write data is receiv ed by the memory controller. the first word can be sent at any time relative to the write command. in this mode, multi-word wr ite command data must be available to the memory controller in sequential cycles. initaref [3:0] defines the number of auto-refres h commands needed by the dram devices to satisfy the initialization sequence. int_ack [4:0] controls the clearing of the int_status parameter. if any of the int_ack bits are set to a "1," the corresponding bit in the int_status parameter will be set to "0." any int_ack bits written with a "0" will not alter the corresponding bit in the int_ status parameter. this parameter will always read back as "0".
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 55 m9999-031810-1.2 int_mask [5:0] active-high mask bits that control the value of the memory controller_int signal on the asic interface. this mask is inverted and then logically and'ed with the output s of the int_status parameter. int_status [5:0] shows the status of all possible in terrupts generated by the memory controller. the msb is the result of a logical or of all the lower bits. this parameter is read-only. note: backwards compatibility is available fo r register parameters across configurations. however, even with this compatibility, the i ndividual bits, their meaning and the size of the int_status parameter may change. the int_status bits corre spond to these interrupts: 0 = a single access outside the defined physical memory space detected. 1 = multiple accesses outside the defi ned physical memory space detected. 2 = dram initialization complete. 3 = address cross page boundary detected. 4 = dll unlock condition detected. 5 = logical or of all lower bits. intrptapburst [0] e nables interrupting an auto pre-charge comm and with another command for a different bank. if enabled, the current operation will be interrupted. however, the bank will be pre- charged as if the current operati on were allowed to continue. 'b0 = disable interrupting an auto pre- charge operation on a different bank. 'b1 = enable interrupting an auto pre- charge operation on a different bank. intrptreada [0] e nables interrupting of a combined read with auto pre-charge comm and with another read command to the same bank before the first read command is completed. 'b0 = disable interrupting the combined read with auto pre-charge command with another read command to the same bank. 'b1 = enable interrupting the combined read with auto pre-charge command with another read command to the same bank. intrptwritea [0] enables interrupting of a combined write with auto pre-char ge command with another read or write command to the same bank before the first write command is completed. 'b0 = disable interrupting a combined write with auto pre-charge command with another read or write command to the same bank. 'b1 = enable interrupting a combined write wi th auto pre-charge co mmand with another read or write command to the same bank. max_col_reg [3:0] defines the maximum width of co lumn address in the dram devices. this value can be used to set the column_size paramet er. this parameter is read-only. column_size = max_col_reg - . max_cs_reg [1:0] defines the maximum number of chip se lects for the memory cont roller as the log2 of the number of chip selects. max_row_reg [3:0] defines the maximum width of t he memory address bus (number of row bits) for the memory controller. this value can be used to set the addr_pins param eter. this parameter is read-only. addr_pins = max_row_reg - . no_cmd_init [0] disables dram comm ands until dll initialization is complete and tdll has expired. 'b0 = issue only ref and pre commands during dll initialization of the dram devices. 'b1 = do not issue any type of command during dll initialization of the dram devices. out_of_range_addr [30: 0] holds the address of the command that caused an out-of-range in terrupt request to the memory devices. this parameter is read-only. out_of_range_length [9:0] holds the l ength of the command that caused an out-of-range in terrupt request to the memory devices. this parameter is read-only.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 56 m9999-031810-1.2 out_of_range_source_id [2:0] holds the source id of the comm and that caused an out -of-range interrupt request to the memory devices. this parameter is read-only out_of_range_type [1:0] holds the type of comm and that caused an out-of-range inte rrupt request to the memory devices. this parameter is read-only placement_en [0] e nables using the placement l ogic to fill the command queue. 'b0 = placement logic is disabled. the command queue is a straight fifo. 'b1 = placement logic is enabled. the co mmand queue will be filled according to the placement logic factors. port_busy [7:0] indicates that a port is actively processing a comm and. each bit controls the corresponding port. this parameter is read-only. 'b0 = port is not busy. 'b1 = port is busy. power_down [0] w hen this parameter is written with a "1", the memory controller will complete processing of the current burst for the current transaction (if any), i ssue a pre-charge all command and then disable the clock enable signal to t he dram devices. any subsequent commands in the command queue will be suspended until this par ameter is written with a "0". 'b0 = enable full power state. 'b1 = disable the clock enable and power down the memory controller. priority_en [0] e nables priority as a condition when using the placement logic to fill the command queue. 'b0 = disabled 'b1 = enabled q_fullness [1:0] defines quantity of data that will be considered full for the command queue. reduc [0] controls the width of the memory dat apath. when enabled, the upper half of the memory buses (dq, dqs and dm) are unused and relevant data only exists in the lower half of the buses. this parameter expands the databahn memory controller for use with memory devices of the confi gured width or half of the configured width. note: the entire user datapath is used regardless of this setting. when operating in half datapath mode, only bstlen values of 4 and 8 are supported. 'b0 = standard operation using full memory bus. 'b1 = memory datapath width is half of the maximum size. reg_dimm_enable [0] e nables registered dimm operations to control the address and command pipeline of the memory controller. 'b0 = normal operation 'b1 = enable registered dimm operation rw_same_en [0] e nables read/write grouping as a condition when using the placement logic to fill the command queue. 'b0 = disabled 'b1 = enabled
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 57 m9999-031810-1.2 srefresh [0] when this parameter is written with a 'b1, the dram device(s) w ill be placed in self-refresh mode. for this, the current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh command will be issued to the dram, and the clock enable signal will be de-asserted. the system will remain in self-refresh mode unt il this parameter is written with a 'b0. the dram devices will re turn to normal operating mode after the self- refresh exit time (txsr) of t he device and any dll initialization time for the dram is reached. the memory controller will resume processing of the commands from the interruption point. this parameter will be updated with an assertion of the srefresh_enter pi n, regardless of the behavior on the register interfac e. to disable self-refresh agai n after a srefresh_enter pin assertion, the user will need to clear the parameter to 'b0. 'b0 = disable self-refresh mode. 'b1 = initiate self-refresh of the dram devices. start [0] with this parameter set to 'b0, the me mory controller will not issue any commands to the dram devices or respond to any signal activity except for reading and writing parameters. once this parameter is set to 'b1, the memory controller will respond to inputs from the asic. when set, the memory controller begins its initializ ation routine. when t he interrupt bit in the int_status parameter associated with complet ed initialization is set, the user may begin to submit transactions. 'b0 = controller is not in active mode. 'b1 = initiate active mode for the memory controller. tcke [2:0] defines the minimum cke pulse width, in cycles. tdal [3:0] defines the auto pre-charge write recovery time when auto pre-charge is enabled (ap is set), in cycles. this is defined internally as trp (pre-charge time) + auto pre-charge write recovery time. note that not all memories use this par ameter. if tdal is defined in the memory specification, then pr ogram this parameter to the s pecified value. if the memory does not specify a tdal time, then program this parameter to twr + trp. do not program this parameter with a value of 0x0 or the memory controller will not function properly when aut o pre-charge is enabled. tdll [15:0] defines the dram dll lock time, in cycles. temrs [1:0] defines the dram extended m ode parameter set time, in cycles. tinit [23:0] defines the dram in itialization time, in cycles. tmrd [4:0] defines the dram mode regi ster set command time, in cycles. tpdex [2:0] defines the dram power-dow n exit command period, in cycles. tras_lockout [0] defines the tras lockout setti ng for the dram device. tras lockout allows the memory controller to execute auto pr e-charge commands bef ore the tras_min parameter has expired. 'b0 = tras lockout not supported by memory device. 'b1 = tras lockout supported by memory device. tras_max [15:0] defines the dram ma ximum row active time, in cycles. tras_min [7:0] defines the dram mini mum row activate time, in cycles. trc [4:0] defines the dram period between active commands for the same bank, in cycles. trcd_int [7:0] defines the dram ras to cas delay, in cycles tref [11:0] defines the dram cycles between refresh commands. trfc [7:0] defines the dram re fresh command time, in cycles. trp [3:0] defines the dram pre-charge command time, in cycles. trrd [2:0] defines the dram ac tivate to activate delay for different banks, in cycles. twr_int [2:0] defines the dram wr ite recovery time, in cycles.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 58 m9999-031810-1.2 twtr [2:0] sets the number of cycles needed to switch from a write to a read operation, as dictated by the ddr s dram specification. txsnr [15:0] defines the dram txsnr parameter, in cycles. txsr [15:0] defines the dram self -refresh exit time, in cycles. version [15:0] holds the version number for th is controller. this parameter is read-only. wr_dqs_shift [6:0] sets the delay for the clk_wr signal to ensure correct data c apture in the i/o logic. each increment of this par ameter adds a delay of 1/128 of the system clock. the same delay will be added to the clk_dqs_out signal for each slice. wr_dqs_shift_bypass [6:0] sets the delay for the clk_wr signal when the dll is being bypassed. this is used to ensure correct data capture in the i/o logic. the value programmed into this paramet er sets the actual number of delay elements in the clk_wr line. if the to tal delay time programmed exceeds the number of delay elements in the delay chain, then the delay will be set internally to the maximum number of delay elements available. write_modereg [0] supplies the emrs data for each ch ip select to allow individual chips to set masked refreshing. when this parameter is written with a 'b1, the mode parameter(s) [emrs register] within t he dram devices will be written. each subsequent write_modereg setting will write t he emrs register of the next chip select. this parameter will always read back as 'b0. the mode registers are autom atically written at initialization of the memory controller. there is no need to initiate a mode register write after setting the start parameter in the memory controller unle ss some value in these registers needs to be changed after initialization. writeinterp [0] defines whether the memory cont roller can interrupt a write burst with a read command. some memory devices do not allow this functionality. 'b0 = the device does not support read commands interrupting write commands. 'b1 = the device does support read co mmands interrupting write commands. 2.5 static memory controller register (0x5000-0x5fff) 2.5.1 external i/o access control register 0(extacon0 offset 0x5000) the system has three external i/o access control registers that control external i/o banks. these registers correspond to the three external i/o banks that are supported by the ksz8692mpb/KSZ8692XPB. external i/o access cycles are controlled through these registers( extacon0, extacon1, extacon2), or through an external wait signals, ewaitn. the delay times of the c ontrol signals (oen, wben, ecsn) can be programmed to obtain access cycles that are longer than thos e possible with a specified value. the following table shows the extacon0 register bit fields. bit field default value read/ write description 31:30 0 ro reserved 29:22 - rw eb0nptr external i/o bank 0 last address pointer this value is the current bank end addre ss. the last address is calculated as {eb0nptr, 0xffff}. 21:20 0 ro reserved 19:12 - rw eb0bptr external i/o bank 0 base pointer this value is the start address of the ex ternal i/o bank 0. the start address is calculated as eb0bptr << 16.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 59 m9999-031810-1.2 11:9 - rw eb0tact external i/o bank 0 wr ite enable/output enable active time the access time for bank 0 is defined in unit of system clock. tmult = 0 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles tmult > 0 000 = 2^(tmult + 3) cycles 001 = 1 x 2^tmult + 2^(tmult + 3) cycles 010 = 2 x 2^tmult + 2^(tmult + 3) cycles 011 = 3 x 2^tmult + 2^(tmult + 3) cycles 100 = 4 x 2^tmult + 2^(tmult + 3) cycles 101 = 5 x 2^tmult + 2^(tmult + 3) cycles 110 = 6 x 2^tmult + 2^(tmult + 3) cycles 111 = 7 x 2^tmult + 2^(tmult + 3) cycles note: see ergcon register for tmult definition. 8:6 - rw eb0tcoh external i/o b ank 0 chip select hold time the chip select hold time for bank 0 is defined in unit of system clock. 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles 5:3 - rw eb0tacs external i/o bank 0 address setup time before ecsn the address setup time for bank 0 is defined in unit of system clock. 000 = 0 cycle 001 = tmult + 1 cycles 010 = 2 x tmult + 2 cycles 011 = 3 x tmult + 3 cycles 100 = 4 x tmult + 4 cycles 101 = 5 x tmult + 5 cycles 110 = 6 x tmult + 6 cycles 111 = 7 x tmult + 7 cycles 2:0 - rw eb0tcos external i/o bank 0 chip select setup time before oen the chip select setup time for bank 0 is defined in unit of system clock. 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 60 m9999-031810-1.2 2.5.2 external i/o access control register 1(extacon1 offset 0x5004) bit field default value read/ write description 31:30 00 ro reserved 29:22 - rw eb1nptr external i/o bank 1 last address pointer this value is the current bank end addre ss. the last address is calculated as {eb1nptr, 0xffff}. 21:20 00 ro reserved 19:12 - rw eb1bptr external i/o bank 1 base pointer this value is the start address of the ex ternal i/o bank 1. the start address is calculated as eb1bptr << 16. 11:9 - rw eb1tact external i/o bank 1 wr ite enable/output enable active time the access time for bank 1 is defined in unit of system clock. tmult = 0 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles tmult > 0 000 = 2^(tmult + 3) cycles 001 = 1 x 2^tmult + 2^(tmult + 3) cycles 010 = 2 x 2^tmult + 2^(tmult + 3) cycles 011 = 3 x 2^tmult + 2^(tmult + 3) cycles 100 = 4 x 2^tmult + 2^(tmult + 3) cycles 101 = 5 x 2^tmult + 2^(tmult + 3) cycles 110 = 6 x 2^tmult + 2^(tmult + 3) cycles 111 = 7 x 2^tmult + 2^(tmult + 3) cycles note: see ergcon register for tmult definition. 8:6 - rw eb1tcoh external i/o b ank 1 chip select hold time the chip select hold time for bank 1 is defined in unit of system clock. 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 61 m9999-031810-1.2 5:3 - rw eb1tacs external i/o bank 1 address setup time before ecsn the address setup time for bank 1 is defined in unit of system clock. 000 = 0 cycle 001 = tmult + 1 cycles 010 = 2 x tmult + 2 cycles 011 = 3 x tmult + 3 cycles 100 = 4 x tmult + 4 cycles 101 = 5 x tmult + 5 cycles 110 = 6 x tmult + 6 cycles 111 = 7 x tmult + 7 cycles 2:0 - rw eb1tcos external i/o bank 1 chip select setup time before oen the chip select setup time for bank 1 is defined in unit of system clock. 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles 2.5.3 external i/o access control register 2 (extacon2 offset 0x5008) bit field default value read/ write description 31:30 0 ro reserved 29:22 - rw eb2nptr external i/o bank 2 last address pointer this value is the current bank end address. t he last address is calculated as {eb2nptr, 0xffff}. 21:20 0 ro reserved 19:12 - rw eb2bptr external i/o bank 2 base pointer this value is the start address of the external i/o bank 2. the start address is calculated as eb2bptr << 16.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 62 m9999-031810-1.2 11:9 - rw eb2tact external i/o bank 2 wr ite enable/output enable active time the access time for bank 2 is defined in unit of system clock. tmult = 0 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles tmult > 0 000 = 2^(tmult + 3) cycles 001 = 1 x 2^tmult + 2^(tmult + 3) cycles 010 = 2 x 2^tmult + 2^(tmult + 3) cycles 011 = 3 x 2^tmult + 2^(tmult + 3) cycles 100 = 4 x 2^tmult + 2^(tmult + 3) cycles 101 = 5 x 2^tmult + 2^(tmult + 3) cycles 110 = 6 x 2^tmult + 2^(tmult + 3) cycles 111 = 7 x 2^tmult + 2^(tmult + 3) cycles note: see ergcon register for tmult definition. 8:6 - rw eb2tcoh external i/o b ank 2 chip select hold time the chip select hold time for bank 2 is defined in unit of system clock. 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles 5:3 - rw eb2tacs external i/o bank 2 address setup time before ecsn the address setup time for bank 2 is defined in unit of system clock. 000 = 0 cycle 001 = tmult + 1 cycles 010 = 2 x tmult + 2 cycles 011 = 3 x tmult + 3 cycles 100 = 4 x tmult + 4 cycles 101 = 5 x tmult + 5 cycles 110 = 6 x tmult + 6 cycles 111 = 7 x tmult + 7 cycles 2:0 - rw eb2tcos external i/o bank 2 chip select setup time before oen the chip select setup time for bank 2 is defined in unit of system clock. 000 = 1 cycle 001 = tmult + 2 cycles 010 = 2 x tmult + 3 cycles 011 = 3 x tmult + 4 cycles 100 = 4 x tmult + 5 cycles 101 = 5 x tmult + 6 cycles 110 = 6 x tmult + 7 cycles 111 = 7 x tmult + 8 cycles
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 63 m9999-031810-1.2 2.5.4 rom/sram/flash control register 0(romcon0 offset 0x5010) the ksz8692mpb/KSZ8692XPB has two control registers for rom, sram, and flash memory. these registers correspond to the two rom/sram/flash banks supported by the ksz8692mpb/KSZ8692XPB. the following table shows the register bit fields for bank0. bit field default value read/ write description 31:22 1ffh rw rb0nptr rom/sram/flash bank 0 next pointer this value is the current bank end addre ss. the last address is calculated as {rb0nptr, 0xffff}. 21:12 0 rw rb0bptr rom/sram/flash bank 0 base pointer this value is the start address of t he rom/sram/flash bank 0. the start address is calculated as rb0bptr << 16. 11:7 0 ro reserved 6:4 111b rw rb0tacc rom/sram/flash bank 0 access cycle time the access cycle time is defined in unit of system clock. note that the write cycle access time is at least 3 cycles. 000 = 3 cycles if tmult = 0 for write cycles 000 = tmult + 2 cycles if tmult > 0 for write cycles 000 = tmult + 2 cycles for read cycles 001 = 2 x tmult + 3 cycles 010 = 3 x tmult + 4 cycles 011 = 4 x tmult + 5 cycles 100 = 5 x tmult + 6 cycles 101 = 6 x tmult + 7 cycles 110 = 7 x tmult + 8 cycles 111 = 8 x tmult + 9 cycles 3:2 11b rw rb0tpa rom/sram/flash bank 0 page address access time the access cycle time is specified in unit of system clock. 00 = tmult + 2 cycles 01 = 2 x tmult + 3 cycles 10 = 3 x tmult + 4 cycles 11 = 4 x tmult + 5 cycles 1:0 0 rw rb0pmc rom/sram/flash bank 0 page mode configuration the rb0pmc configures the access size in page mode. 00 = normal rom 01 = 4-word page 10 = 8 word page 11 = 16 word page
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 64 m9999-031810-1.2 2.5.5 rom/sram/flash control register 1(romcon1 offset 0x5014) the ksz8692mpb/KSZ8692XPB has two control registers for rom, sram, and flash memory. these registers correspond to the two rom/sram/flash banks supported by the ksz8692mpb/KSZ8692XPB. the following table shows the register bit fields for bank1. bit field default value read/ write description 31:22 - rw rb1nptr rom/sram/flash bank 1 next pointer this value is the current bank end addre ss. the last address is calculated as {rb1nptr, 0xffff}. 21:12 - rw rb1bptr rom/sram/flash bank 1 base pointer this value is the start address of t he rom/sram/flash bank 1. the start address is calculated as rb1bptr << 16. 11:7 0 ro reserved 6:4 - rw rb1tacc rom/sram/flash bank 1 access cycle time the access cycle time is defined in unit of system clock. note that the write cycle access time is at least 3 cycles. 000 = 3 cycles if tmult = 0 for write cycles 000 = tmult + 2 cycles if tmult > 0 for write cycles 000 = tmult + 2 cycles for read cycles 001 = 2 x tmult + 3 cycles 010 = 3 x tmult + 4 cycles 011 = 4 x tmult + 5 cycles 100 = 5 x tmult + 6 cycles 101 = 6 x tmult + 7 cycles 110 = 7 x tmult + 8 cycles 111 = 8 x tmult + 9 cycles 3:2 - rw rb1tpa rom/sram/flash bank 1 page address access time the access cycle time is specified in unit of system clock. 00 = tmult + 2 cycles 01 = 2 x tmult + 3 cycles 10 = 3 x tmult + 4 cycles 11 = 4 x tmult + 5 cycles 1:0 - rw rb1pmc rom/sram/flash bank 1 page mode configuration the rb1pmc configures the access size in page mode. 00 = normal rom 01 = 4-word page 10 = 8 word page 11 = 16 word page
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 65 m9999-031810-1.2 2.5.6 external i/o and rom/sram/flash g eneral register (ergcon offset 0x5020) the ksz8692mpb/KSZ8692XPB supports 8/16-bit external ro m/sram/flash memory and i/o interfaces. by programming this register, the data width of the rom/sr am/flash memory and i/o inte rfaces can be controlled. the following table shows the register bit fields. bit field default value read/ write description 31:30 0 ro reserved 29:28 3h rw tmult external i/o and rom/sram/flash time multiplier 00 = multiply by 0 01 = multiply by 1 10 = multiply by 2 11 = multiply by 3 27:24 0 ro reserved 23:22 0 rw reserved 21:20 0 rw dsx2 data width for external i/o bank 2 00 = disabled 01 = byte ( 8 bits ) 10 = half-word (16 bits) 19:18 0 rw dsx1 data width for external i/o bank 1 00 = disabled 01 = byte ( 8 bits ) 10 = half-word (16 bits) 17:16 0 rw dsx0 data width for external i/o bank 0 00 = disabled 01 = byte ( 8 bits ) 10 = half-word (16 bits) 15:8 0 ro reserved 7:6 0 rw reserved 5:4 0 rw reserved 3:2 0 rw dsr1 data width for rom/sram/flash bank 1 00 = disabled 01 = byte ( 8 bits ) 10 = half-word (16 bits) 1:0 - rw dsr0 data width for rom/sram/flash bank 0 00 = disabled 01 = byte ( 8 bits ) 10 = half-word (16 bits) note: dsr0?s value is derived from b0size[0] upon power on reset. after power on reset, it can be written with 00b to di sable the bank or the value of b0size[0] to enable the bank. any other wr itten values are ignored.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 66 m9999-031810-1.2 2.6 wan dma regi sters (0x6000-0x7fff) 2.6.1 wan mac dma transmit control register (wmdtxc offset 0x6000) the wan mac dma transmit control register establishes the transmit operating modes and commands for the wan port. this register should be one of the last scrs to be written as part of the transmit initialization. the following table shows the register bit fields. bit field default value read/ write description 31 0 wo wmtrst wan dma soft reset when set, the wan mac dma block is reset. all registers in the wan mac dma block will be reset to the default values. 30 ro reserved 29:24 0x00 rw wmtbs wan dma transmit burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the wan mac dma bur st size is limited only by the amount of data stored in the transmit buffer before issuing a bus request. the wmtbs can be programmed with permissible val ues 0,1, 2, 4, 8, 16, or 32. after reset, the wmtbs default is 0, i.e. unlimited. 23:20 0x00 ro reserved 19 0 rw factory test only. must be left as default 0 18 0 rw wmtucg wan mac transmit udp checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct udp checksum for outgoing udp/ip frames at wan port. when this bit is set, add crc should also turn on. 17 0 rw wmttcg wan mac transmit tcp checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct tcp checksum for outgoing tcp/ip frames at wan port. when this bit is set, add crc should also turn on. 16 0 rw wmticg wan mac transmit ip checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct ip checksum for outgoing ip frames at wan port. when this bit is set, add crc should also turn on. 15:10 0x00 ro reserved 16 0 rw wmticg wan mac transmit ip checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct ip checksum for outgoing ip frames at wan port. when this bit is set, add crc should also turn on. 9 0 rw wmtfce wan mac transmit flow control enable when this bit is set and the ksz8692mpb/KSZ8692XPB is in full duplex mode, flow control is enabled and the ksz8692mpb/KSZ8692XPB will transmit a pause frame when the mac dma receive buffer capacity has reached a level that may cause the buffer to overflow. when this bit is set and the ksz8692mpb/KSZ8692XPB is in half duplex mode, back-pressure flow control is enabled. when this bit is cleared, no transmit flow control is enabled. the threshold is defined by the hi watermark of low priority packet in the wan mac rx watermark register.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 67 m9999-031810-1.2 8 0 rw wmtlb wan mac dma loop back mode select the ksz8692mpb/KSZ8692XPB wan port in loopback operation modes. when set, the packet to be sent will be returned at the mac interface. 7:3 0x0 ro reserved 2 0 rw wmtep wan mac dma transmit enable padding when set, the ksz8692mpb/KSZ8692XPB automat ically adds a padding field to a packet shorter than 64 bytes. note: setting this bit automatic ally enables add crc feature. 1 0 rw wmtac wan mac dma transmit add crc when set, the ksz8692mpb/KSZ8692XPB appends the crc to the end of the transmission frame. 0 0 rw wmte wan mac dma tx enable when the bit is set, the mdma tx block is enabled and placed in a running state. when reset, the transmission proce ss is placed in the stopped state after completing the transmission of the cu rrent frame. the stop transmission command is effective only when the transmi ssion process is in the running state. 2.6.2 wan mac dma receive control register (wmdrxc offset 0x6004) the wan mac dma receive control regi ster establishes the receive operati ng modes and commands for the wan port. this register should be one of the last scrs to be written as part of the receive initialization. the following table shows the register bit fields. bit field default value read/ write description 31:30 00 ro reserved 29:24 0x00 rw wmrbs wan dma receive burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the wan mac dma burst size is limited only by the amound of data stored in the receive buffer before issui ng a bus request. the wmrbs can be programmed with permissible values 0,1, 2, 4, 8, 16, or 32. after reset, the wmrbs default is 0, i.e. unlimited. 23:20 0x00 ro reserved 19 0 rw wihae wan ip header alignment enable when set, ksz8692mpb/KSZ8692XPB will align ip header at dword boundary if it?s an ip packet. 18 0 rw wmrucc wan mac receive udp checksum check when set, ksz8692mpb/KSZ8692XPB will check for correct udp checksum for incoming udp/ip frames at wan port. packets rece ived with incorrect udp checksum will be discarded. 17 0 rw wmrtcg wan mac receive tcp checksum check when set, the ksz8692mpb/KSZ8692XPB will che ck for correct tcp checksum for incoming tcp/ip frames at wan port. packets received with incorrect tcp checksum will be discarded. 16 0 rw wmricg wan mac receive ip checksum check when set, the ksz8692mpb/KSZ8692XPB will c heck for correct ip checksum for incoming ip frames at wan port.packets received with incorrect ip checksum will be discarded. 15 0 rw factory test only. must be left as default 0 14:11 0x00 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 68 m9999-031810-1.2 10 0x0 rw wdlppdc wan drop low priority packet during congestion enable when this bit is set and the transmit flow control (bit9 of mac dma transmit control register) is disabled, the low priority packet will be dropped if the high watermark of low priority packet defined in wan mac rx watermark register is triggerred. ksz8692mpb/KSZ8692XPB will c ontinue dropping the low priority packet till the rx buffer is back to the low watermark state. the following table describes the action of ksz8692m pb/KSZ8692XPB in the corresponding setting: transmit flow control enable drop low priority packet during congestion enable action 0 0 drop both hi and low priority packet when the hi watermark of low priority packet defined in mac rx watermark register is triggerred. 0 1 drop low priority packet when the hi watermark of low priority defined in mac rx watermark register is triggerred. drop both hi and low priority packet when the hi watermark of hi priority defined in mac rx watermark register is triggerred. 1 0 transmit flow control packet (or backpressure) when the hi watermark of low priority packet defined in mac rx watermark register is triggerred. 1 1 transmit flow control packet (or backpressure) when the hi watermark of low priority packet defined in mac rx watermark register is triggerred. note: the classification of the hi/low priority for each packet could be determined by diffserv, 802.1q or access control list rules. 9 0 rw wmrfce wan mac receive flow control enable when this bit is set and the ksz8692mpb/KSZ8692XPB is in full duplex mode, flow control is enabled and the ksz8692mpb/KSZ8692XPB will acknowledge a pause frame from the wan port, i.e., the outgoing packets will be pending in the transmit buffer until the pause contro l timer expires. this field has no meaning in half-duplex mode and should be programmed to 0. when this bit is cleared, no flow control is enabled. 8:7 00 ro reserved 6 0 rw wmrb wan mac receive broadcast when set, the wan mac receive all broadcast frames. 5 0 rw wmrm wan mac receive multicast when set, the wan mac receive all mult icast frames (including broadcast). 4 0 rw wmru wan mac receive unicast when set, the wan mac receive unicast fr ames that match the 48-bit station address of the wan mac.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 69 m9999-031810-1.2 3 0 rw wmre wan mac dma receive error frame when set, the ksz8692mpb/KSZ8692XPB will pa ss the errors frames received to the host. error frames include runt frames, oversized frames, crc errors. note: maximum packet size the wan port can receive is 2015 bytes. any packet larger than 2015 is dropped. 2 0 rw wmra wan mac dma receive all when set, the ksz8692mpb/KSZ8692XPB receives all incoming frames, regardless of its destination address. 1 0 rw wmche multicast hash filter enable when this bit is set, the multicas t hash filtering function is enabled . 0 0 rw wmre wan mac dma rx enable when the bit is set, the dma rx block is enabled and placed in a running state. when reset, the receive process is placed in the stopped state after completing the reception of the curr ent frame. the stop transmission command is effective only when the reception proce ss is in the running state. 2.6.3 wan mac dma transmit start command register (wmdtsc offset 0x6008) this register is written by the the cpu when pa ckets in the wan data buffer need to be transmitted. the following table shows the register bit fields. bit field default value read/ write description 31:0 0x0 wo wtsc wan transmit start command when written with any value, the wa n transmit dma checks for frames to be transmitted. if no descriptor is availabl e, the transmit process returns to suspended state. if descriptiors are available, the transmit process starts or resumes. this bit is self-clearing. 2.6.4 wan mac dma receive start command register (wmdrsc offset 0x600c) this register is written by the the cpu when there are frame data in receive buffer to be processed. the following table shows the register bit fields. bit field default value read/ write description 31:0 0x0 wo wrsc wan receive start command when written with any value, the wan receive dma checks for descriptors to be acquired. if no descriptor is availabl e, the receive process returns to suspended state and wait for the next rece ive restart command. if descriptiors are available, the receive process re sumes. this bit is self-clearing. 2.6.5 wan transmit descriptor list base address register (wtdlb offset 0x6010) this register is used for wan transmit de scriptor list base address register. the regist er is used to point to the start of the appropriate descriptor list. writing to this register is per mitted only when its respective process is in the stopped state . when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be word (32-bit) aligned. the ksz8692mpb/KSZ8692XPB behavior is unpredictable when the lists are not word-aligned.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 70 m9999-031810-1.2 the following table shows the register bit fields. bit field default value read/ write description 31:2 0x0 rw wstl wan start of transmit list note: write can only occur when the transmit process stopped. 1:0 00 ro reserved 2.6.6 wan receive descriptor list base address register (wrdlb offset 0x6014) this register is used for wan receive descriptor list base address register. the register is used to point to the start of the appropriate descriptor list. writing to this register is permitted only when its respective process is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be word (32-bit) aligned. the ksz8692mpb/KSZ8692XPB behavior is unpredictable when the lists are not word-aligned. the following table shows the register bit fields. bit field default value read/ write description 31:2 0x0 rw wsrl wan start of receive list note: write can only occur when the transmit process stopped. 1:0 00 ro reserved 2.6.7 wan mac station address low register (wmal offset 0x6018) station address is used to define the individual destination address the ksz8692mpb/KSZ8692XPB wan port will respond to when receiving frames. network addresses are gener ally expressed in the form of 01:23:45:67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit field default value read/ write description 31:0 0x0 rw wmal wan mac station address low 4 bytes the least significant word of the wan mac station address. 2.6.8 wan mac station address high register (wmah offset 0x601c) station address is used to define the individual destination address the ksz8692mpb/KSZ8692XPB wan port will respond to when receiving frames. network addresses are gener ally expressed in the form of 01:23:45:67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 15:0 0x0 rw wmal wan mac station address high 2 bytes the most significant word of the wan mac station address.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 71 m9999-031810-1.2 2.6.9 wan mac misc. control register (wemc offset 0x6020) the ksz8692mpb/KSZ8692XPB port 0 support 10/100 mbps ethernet speed and some configuration modes are shown in the following table bit field default value read/ write description 30:16 0x0 ro reserved 15 0x1 rw factory reserved 14 0x1 rw factory reserved 13 0x0 rw factory test only. must be left as default 0 12 0x0 rw mac/phy mii mode select 0: mac mii mode 1: phy mii mode 11 0x0 rw mode select 0: mii mode is select (default) 1: factory reserved 10 0x0 ro reserved 9 0x0 rw frame length check 8 0x1 rw excessive defer enable 7 0x1 rw receive enable 6 0x0 rw shortcut slot time counter 5 0x0 rw transmit half duplex flow control mode 2 enable 4 0x0 rw no excessive collision 3 0x0 rw transmit collision limit 4 (super mac enable) when set, the ksz8692mpb/KSZ8692XPB collision back off algorithm will always limit the backoff timer to within 2^4 2:1 0x0 rw port 0 speed select 00: 10mbps 01: 100mbps 10: factory reserved 11: reserved 0 0x 0 rw duplex mode select 1: fullduplex mode, 0: half duplex mode. note: when ksz8692mpb/KSZ8692XPB is at 1gbps speed, only full-duplex mode is support. both the full-duplex and half -duplex modes are supported at 100/10 mbps speed.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 72 m9999-031810-1.2 2.6.10 factory reserved (wmipgl offset 0x 6068) 2.6.11 wan mac rx watermark register (wmwtr : offset 0x6028) the ksz8692mpb/KSZ8692XPB supports 8kb receive buffer size at wan port. the following table shows the register bit fields. bit field default value read/ write description 31:27 0x0 ro reserved 26:20 0x70 rw high watermark of high priori ty packet (7k), 64 byte is the base unit 19:17 0x0 ro reserved 16:10 0x50 rw high watermark of low priori ty packet (5k), 64 byte is the base unit 9:7 0x0 ro reserved 6:0 0x20 rw low watermark (2k), 64 byte is the base unit 2.6.12 an mac multicast table low register (wmtrl: offset 0x602c) the 64 bit multicast table is used for group address filtering. the has value is defined as the six most significant bits of th e crc of the da. the most significant bits select the register to be used, while t he other determines the bit within the register. the following table shows the register bit fields. bit field default value read/ write description 31:0 0 rw wmtrl multicast table low when appropriate bit is set, the packet received with da matches the crc hashing function is receiv ed without being filtered. note: when the receive all (rxra) or rece ive multicast (rxrm) bit is set in the rxcr then all multicast addresses are rece ived regardless of t he multicast table value. 2.6.13 wan mac multicast table high register (wmtrh: offset 0x6030) the 64 bit multicast table is used for group address filtering. the has value is defined as the six most significant bits of th e crc of the da. the most significant bits select the register to be used, while the other determines the bit within the register. the following table shows the register bit fields. bit field default value read/ write description 31:0 0 rw wmtrh multicast table high when appropriate bit is set, the packet received with da matches the crc hashing function is receiv ed without being filtered. note: when the receive all (rxra) or rece ive multicast (rxrm) bit is set in the rxcr then all multicast addresses are rece ived regardless of t he multicast table value.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 73 m9999-031810-1.2 2.6.14 wan wakeup frame control register (wwfcr : offset 0x6034) this register holds control information programmed by the cpu to control the transmit module function. bit field default value read/ write description 15:8 0x00 ro reserved. 7 0 rw mprxe magic packet rx enable when set, it enables the magic packet pattern detection. when reset, the magic packet pattern detection is disabled. 6:4 0x0 ro reserved. 3 0 rw wf3e wake up frame 3 enable when set, it enables the wake up frame 3 pattern detection. when reset, the wake up frame pattern detection is disabled. 2 0 rw wf2e wake up frame 2 enable when set, it enables the wake up frame 2 pattern detection. when reset, the wake up frame pattern detection is disabled. 1 0 rw wf1e wake up frame 1 enable when set, it enables the wake up frame 1 pattern detection. when reset, the wake up frame pattern detection is disabled. 0 0 rw wf0e wake up frame 0 enable when set, it enables the wake up frame 0 pattern detection. when reset, the wake up frame pattern detection is disabled. 2.6.15 wan wakeup frame 0 crc register (wwf0crc: offset 0x6038) this register contains the expected crc va lues of the 1st wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw wwf0crc wake up frame 0 crc the expected crc value of a wake up frame 0 pattern. 2.6.16 wan wakeup frame 0 mask 0 register (wwf0mk0 : offset 0x603c) this register contains the first 32 byte mask values of the 1st wake up frame pattern. bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw wwf0bm0 wake up frame 0 mask 0 the first 32 byte mask of a wake up frame pattern. 2.6.17 wan wakeup frame 0 mask 1 register (wwf0mk1: offset 0x6040) this register contains the next 32 byte mask values of the 1st wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 74 m9999-031810-1.2 bit field default value read/ write description 31:0 -- rw wwf0bm1 wake up frame 0 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern. 2.6.18 wan wakeup frame 1 crc register (wwf1crc: offset 0x6044) this register contains the expected crc values of the 2nd wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw wwf1crc wake up frame 1 crc the expected crc value of a wake up frame 0 pattern. 2.6.19 wan wakeup frame 1 mask 0 register (wwf1mk0 : offset 0x6048) this register contains the first 32 byte mask values of the 2nd wake up frame pattern. bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw wwf1bm0 wake up frame 1 mask 0 the first 32 byte mask of a wake up frame pattern. 2.6.20 wan wakeup frame 1 mask 1 register (wwf1mk1: offset 0x604c) this register contains the next 32 byte mask values of the 2nd wake up frame pattern. bit 0 selects the 33 th byteof the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw wwf1bm1 wake up frame 1 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern. 2.6.21 wan wakeup frame 2 crc register (wwf2crc: offset 0x6050) this register contains the expected crc va lues of the 3rd wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw wwf2crc wake up frame 2 crc the expected crc value of a wake up frame 0 pattern.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 75 m9999-031810-1.2 2.6.22 wan wakeup frame 2 mask 0 register (wwf2mk0 : offset 0x6054) this register contains the first 32 byte mask values of the 3rd wake up frame pattern. bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw wwf2bm0 wake up frame 2 mask 0 the first 32 byte mask of a wake up frame pattern. 2.6.23 wan wakeup frame 2 mask 1 register (wwf2mk1: offset 0x6058) this register contains the next 32 byte mask values of the 3rd wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw wwf2bm1 wake up frame 2 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern. 2.6.24 wan wakeup frame 3 crc register (wwf3crc: offset 0x605c) this register contains the expected crc va lues of the 4th wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw wwf3crc wake up frame 3 crc the expected crc value of a wake up frame 0 pattern. 2.6.25 wan wakeup frame 3 mask 0 register (wwf3mk0: offset 0x6060) this register contains the first 32 byte mask values of the 4th wake up frame pattern . bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw wwf3bm0 wake up frame 3 mask 0 the first 32 byte mask of a wake up frame pattern. 2.6.26 an wakeup frame 3 mask 1 register (wwf3mk1: offset 0x6064) this register contains the next 32 byte mask values of the 4th wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw wwf3bm1 wake up frame 3 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 76 m9999-031810-1.2 2.6.27 wan broadcast traffic control register (wbtc: offset 0x60e4) this register is used to regulate t he broadcast traffic which could possibly overwhelm the maximum cpu bandwidth in absorbing the ethernet traffic if no protecti on mechanism is provided. bit31 is the c ontrol bit to enable this function if it?s configured to 1. bit7-0 provides an 8-bit preload value to a decrement counter. when the incoming packet is a broadcast packet, the device will pass the packet if the current counter value is zero. if not zero, the broadcast packet will be dropped. no matter broadcast is passed or dr opped the counter is decremented by 1. t herefore, if the preload value is 1, half of the broadcast packets will be passed. if the preload val ue is 2, one third of the broadcast packets will be passed. the default setting is zero, which means device will accept all the broadcast traffic after power-on. the following table shows the bit fields of wbtc register. bit field default value read/ write description 31 0 rw wbtce wan broadcast traffic control enable: 1: enable 0: disable 30-8 0x0 ro reserved 7:0 0x0 rw wbtcplv wan broadcast traffic control preload value it?s value ranges from 0 to 255. 2.6.28 wan packet dropped count register (wpdc: offset 0x60e8) this register is used to record the number of packet dropped due to the following reasons: 1. wan port receive buffer overrun 2. wan port acl filtering 3. wan port broadcast traffic control this register is cleared after read. the following table shows the bit fields of wpdc register. bit field default value read/ write description 31-0 0 rw wpdcv wan packet dropped count value 2.6.29 wan checksum error packet dropped count register (wcepdc: offset 0x60ec) this register is used to record the number of packet dropped due to the following reasons: 1. ip header checksum error 2. tcp checksum error 3. udp checksum error 4. icmp checksum error note: this counter is recommended for ipv4 systems only. this register is cleared after read. the following table shows the bit fields of wcepdc register. bit field default value read/ write description 31-0 0 rw wcepdcv wan checksum error packet dropped count value
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 77 m9999-031810-1.2 2.6.30 wan access control list 1 data register (wacl1d: offset 0x6100) wan access control list 2 data register (wacl2d: offset 0x6110) ? ? ? ? ? ? ? ? wan access control list 16 data register (wacl16d: offset 0x61f0) wan access control list 17 data register (wacl17d: offset 0x6104) wan access control list 18 data register (wacl18d: offset 0x6114) ? ? ? ? ? ? ? ? wan access control list 32 data register (wacl32d: offset 0x61f4) the acl function includes 32 acl data registers, 32 acl ma sk registers, and 32 acl confi guration registers to make up 32 rules for mac address (sa only), 32 rules or ipv4 header, and 8 rules for ipv6 header. for acl on mac address (sa) or ipv4 header, each rule is made up of 1 acl data register, 1 acl mask register, and 1 acl configuration register. each rule can be progr ammed independently to support acl on mac or acl on ipv4 header. for acl on ipv6, these each rule is supported by a group made up of 4 consecutive-address data registers, 4 consecutive-address mask registers, and 4 consecutive-address configurat ion registers. each group can be programmed independently to support acl on ipv6 header. the wan access control list data register is used to configure the searched 32-bi t or part of 128-bit data pattern in the acl for mac address acl, 48-bit data pattern [47:0] = {wac l1m[15:0], wacl1d} for rule 1, ?, {wacl32m[15:0], wacl32d} for rule 32. no mask r egisters for mac address acl. for ipv4 rule, the 32-bit data pattern [31:0] = wacl1d for rule 1, ?, wacl32d for rule 32. for ipv6 rule, the 128-bit data pattern [127:0] = {wacl4d, wacl3d, wacl2d, wacl1d} for rule 1, ?, {wacl32d, wacl31d, wacl30d, wacl29d} for rule 8. the following table shows the bit fields of wacl1d register. bit field default value read/ write description 31-0 0 rw wacl1d wan access control list data pattern 2.6.31 wan access control list 1 mask register (wacl1m: offset 0x6108) wan access control list 2 mask r egister (wacl2m: offset 0x6118) ? ? ? ? ? ? ? ? wan access control list 16 mask r egister (wacl16m: offset 0x61f8) wan access control list 17 mask register (wacl17m: offset 0x610c) wan access control list 18 mask register (wacl18m: offset 0x611c) ? ? ? ? ? ? ? ? wan access control list 32 mask register (wacl32m: offset 0x61fc) this register is used to configure the mask value of the searched 32-bit or part of 128-bit data pattern in the access control list. for mac address acl, 48-bit data pattern [47:0] = {w acl1m[15:0], wacl1d} for rule 1, ?, {wacl32m[15:0], wacl32d} for rule 32. no mask r egisters for mac address acl. for ipv4 rule, the 32-bit data mask [31:0] = wa cl1m for rule 1, ?, wacl32m for rule 32. for ipv6 rule, the 128-bit data mask [127:0] = {wacl4m , wacl3m, wacl2m, wacl1m} for rule 1, ?, {wacl32m, wacl31m, wacl30m, wacl29m} for rule 8. the following table shows the bit fields of wacl1m register. bit field default value read/ write description 31-0 0 rw wacl1m wan access control list mask value
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 78 m9999-031810-1.2 2.6.32 wan access control list 1 configuration register (wacl1c: offset 0x6200) wan access control list 2 configurat ion register (wacl2c: offset 0x6210) ? ? ? ? ? ? ? ? wan access control list 16 configurat ion register (wacl16c: offset 0x62f0) wan access control list 17 configuration register (wacl17c: offset 0x6204) wan access control list 18 configuration register (wacl18c: offset 0x6214) ? ? ? ? ? ? ? ? wan access control list 32 configurat ion register (wacl32c: offset 0x62f4) this register is used to c onfigure the access control list. for mac address acl, wacl1c is for ru le 1, ?, wacl32c is for rule 32. for ipv4 rule, wacl1c is for rule 1, ?, wacl32c is for rule 32. for ipv6 rule, wacl1c, wacl5c, wa cl9c, wacl13c, wacl17c, wacl21c, wa cl25c, wacl29c are used for rule 1, 2, 3, 4, 5, 6, 7 and 8 respectively. other wacl configuration registers are not used. the following table shows the bit fields of wacl1c register. bit field default value read/ write description 31 0 rw aclon when this bit is set, the access control list 1 is enabled. 30 0 rw ipv6s. this bit tells the acl is on ipv4 or ipv6. this bit is active only when macs = 0. when this bit is cleared, the systems is ipv4 systems, alc has 32 rules. each wacl configuration register can be programmed independently. when this bit is set, the systems is ipv6 systems, acl has 8 rules. note that this bit can only be set in registers wacl1c, wacl5c, wacl9c, wacl13c, wacl17c, wacl21c, wacl25c, wacl29c for rule 1, 2, 3, 4, 5, 6, 7 and 8 respectively for an ipv6 acl. fo r example, once the bit wacl1c[30] is set, then bit wacl2c[30], wacl3c[30], wa cl4c[30] have no effect in order to avoid conflict on ipv6 rule 1; ?; once the bit wacl29c[30] is set, then bit wacl30c[30], wacl31c[30], wacl32c[30] have no effect in order to avoid conflict on ipv6 rule 8. 29 0 rw macs. the mac address is sa only when this bit is cleared, the acl is for ipv4/ipv6 address. when this bit is set, the acl is for mac address (sa only). 28:20 0 ro reserved 19 0 rw flton. enable filter on the packet that matches the configured data pattern. 18:17 0 ro reserved 16 0 rw hipri when this bit is set, the pa cket that matches with the configured data pattern will be marked as hi priority packet. 15 0 rw offsets when this bit is set, the o ffset address scheme is used for data match. the fstbt_ptr defined in bit5:0 is used as the first byte pointer. this is only valid when acl1on (bit31) is set. 14 0 rw ipv6sips when this bit is set, the 128-bit source ip address matching is enabled. this bit is valid only when the valid ipv6s (bit30) is set. note that this bit can only be programmed in registers wacl1c, wacl5c, wacl9c, wacl13c, wacl17c, wacl21c, wacl25c, wacl29c for rule 1, 2, 3, 4, 5, 6, 7 ,8 respectively for an ipv6 acl. for example, once the bit wacl1c[14] is programmed, then bit wacl2c[14], wacl3c[14], wacl4c[14] have no effect in order to avoid conflic t on ipv6 rule 1; ?; once the bit wacl29c[14] is programmed, t hen bit wacl30c[14], wacl31c[14], wacl32c[14] have no effect in order to avoid conflict on ipv6 rule 8.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 79 m9999-031810-1.2 13 0 rw ipv6dips when this bit is set, t he 128-bit destination ip address matching is enabled. this bit is valid only when the valid ipv6s (bit30) is set. note that this bit can only be programmed in registers wacl1c, wacl5c, wacl9c, wacl13c, wacl17c, wacl21c, wacl25c, wacl29c for rule 1, 2, 3, 4, 5, 6, 7 ,8 respectively for an ipv6 acl. for example, once the bit wacl1c[13] is programmed, then bit wacl2c[13], wacl3c[13], wacl4c[13] have no effect in order to avoid conflic t on ipv6 rule 1; ?; once the bit wacl29c[13] is programmed, t hen bit wacl30c[13], wacl31c[13], wacl32c[13] have no effect in order to avoid conflict on ipv6 rule 8. 12 0 rw procs when this bit is set, the 8-bit protocol field matching is enabled. once procs is on, the other select bits s hould be off and only the bit7-0 of data and mask registers are used. 11 0 rw spts when this bit is set, the 16-bit source port number matching is enabled. once spts is on, the other select bits should be off except dpts and only the bit15-0 of data and m ask registers are used. 10 0 rw dpts when this bit is set, the 16- bit destination port number matching is enabled. once dpts is on, the other select bi ts should be off except spts and only the bit15-0 of data and m ask registers are used. 9 0 rw ipv4sips when this bit is set, the 32-bit source ip address matching is enabled. once ipv4sips is on, the other select bi ts should be off except ipv4dips. this bit is valid only when ipv6s (bit30) is cleared. 8 0 rw ipv4dips when this bit is set, t he 32-bit destination ip address matching is enabled. once ipv4dips is on, the other select bits should be off except ipv4sips. this bit is valid onl y when ipv6s (bit30) is cleared. 7:6 0 ro reserved 5:0 0 rw fstbt_ptr this value indicates the fi rst byte location in the packet for the 32-bit data pattern maching. for instance, if the value is 0, the 1st/ 2nd/3rd/4th bytes of the packet will be used for comparision. if the value is 12, t he 13th/14th/ 15th/16th bytes of the packet will be used for comparision. 2.6.33 wan diff-serv priority control register 0 (wdspc0: offset 0x6300) the diff-serv priority control registers implement a fully decoded 64-bit dscp (differentiated service code point) to determine priority from the 6 bits of tos field in the ipv4/ip v6 header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that resu lts is compared against the corresponding bit in the dscp register. if the register bit is a 1, the priority is high; if it is a 0, the priority is low. the following table shows the bit fields of wdspc0 register. bit field default value read/ write description 31 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x1f 30 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x1e 29 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x1d 28 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x1c
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 80 m9999-031810-1.2 27 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x1b 26 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x1a 25 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x19 24 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x18 23 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x17 22 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x16 21 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x15 20 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x14 19 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x13 18 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x12 17 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x11 16 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x10 15 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x0f 14 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x0e 13 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x0d 12 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x0c
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 81 m9999-031810-1.2 11 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x0b 10 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x0a 9 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x09 8 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x08 7 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x07 6 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x06 5 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x05 4 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x04 3 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x03 2 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x02 1 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x01 0 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x00
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 82 m9999-031810-1.2 2.6.34 wan diff-serv priority control register 1 (wdspc1: offset 0x6304) the diff-serv priority control registers implement a fully decoded 64-bit dscp (differentiated service code point) to determine priority from the 6 bits of tos field in the ipv4/ip v6 header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that resu lts is compared against the corresponding bit in the dscp register. if the register bit is a 1, the priority is high; if it is a 0, the priority is low. the following table shows the bit fields of wdspc1 register. bit field default value read/ write description 31 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x3f 30 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x3e 29 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x3d 28 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x3c 27 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x3b 26 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x3a 25 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x39 24 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x38 23 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x37 22 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x36 21 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x35 20 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x34 19 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x33
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 83 m9999-031810-1.2 18 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x32 17 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x31 16 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x30 15 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2f 14 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2e 13 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2d 12 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2c 11 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2b 10 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2a 9 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x29 8 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x28 7 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x27 6 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x26 5 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x25 4 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x24 3 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x23
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 84 m9999-031810-1.2 2 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x22 1 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x21 0 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x20 2.6.35 wan diff-serv priority control register 2 (wdspc2: offset 0x6308) the following table shows the bit fields of wdspc2 register. bit field default value read/ write description 31:1 0x0 ro reserved 0 0 rw ip diff-serv priority enable when set, the priority of the incoming packet based on ip diffserv is active. when cleared, no priority decision is based on ip diffserv. 2.6.36 wan tag priority control register (wtpc: offset 0x630c) this register is used to map the 3-bit tag priority value of a frame to a defined priority. if the register bit is a 1, the pri ority is high; if it is a 0, the priority is low. the following table shows the bit fields of wtpc register. bit field default value read/ write description 31:9 0x0 ro reserved 8 0 rw ieee 802.1p enable when set, the priority of the incoming packet based on tag priority is active. when cleared, the tag priori ty function is disabled. 7 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x7 6 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x6 5 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x5 4 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x4 3 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x3
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 85 m9999-031810-1.2 2 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x2 1 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x1 0 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x0 2.7 lan dma regi sters (0x8000-0x9fff) 2.7.1 lan mac dma transmit control register (lmdtxc offset 0x8000) the lan mac dma transmit control regi ster establishes the transmit operati ng modes and commands for the lan port. this register should be one of the last scrs to be written as part of the transmit initialization. the following table shows the register bit fields. bit field default value read/ write description 31 0 wo lmtrst lan dma soft reset when set, the lan mac dma block is reset. all registers in the lan mac dma blo ck will be reset to the default values. 30 0 ro reserved 29:24 0x00 rw lmtbs lan dma transmit burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the lan mac dma burst size is limited only by the amount of data stored in the transmit buffer befor e issuing a bus request. the lmtbs can be programmed with permissible values 0,1, 2, 4, 8, 16, or 32. after reset, the lmtbs defaul t is 0, i.e. unlimited. 23:20 0x00 ro reserved 19 0 rw factory test only. must be left as default 0 18 0 rw lmtucg lan mac tr ansmit udp checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct udp checksum for outgoing udp/ip frames at lan port. when this bit is set, add crc should also turn on. 17 0 rw lmttcg lan mac transmit tcp checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct tcp checksum for outgoing tcp/ip frames at lan port. when this bit is set, add crc should also turn on. 16 0 rw lmticg lan mac transmit ip checksum generate when set, the ksz8692mpb/KSZ8692XPB will gener ate correct ip checksum for outgoing ip frames at lan port. when this bit is set, add crc should also turn on. 15:10 0x00 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 86 m9999-031810-1.2 9 0 rw lmtfce lan mac transmit flow control enable when this bit is set and the ksz8692mpb/KSZ8692XPB is in full duplex mode, flow control is enabled and the ksz8692mpb/KSZ8692XPB will transmit a pause frame when the mac dma receive buffer capacity has reached a level that may cause the buffer to overflow. when this bit is set and the ksz8692mpb/KSZ8692XPB is in half duplex m ode, back-pressure flow control is enabled. when this bit is cleared, no tr ansmit flow control is enabled. the threshold is defined by the hi watermark of low priority packet in the lan mac rx watermark register. 8 0 rw lmtlb lan mac dma loop back mode select the ksz8692mpb/KSZ8692XPB lan port in loopback operation modes. when set, the packet to be sent will be returned at the mac interface. 7:3 0x0 ro reserved 2 0 rw lmtep lan mac dma transmit enable padding when set, the ksz8692mpb/KSZ8692XPB automat ically adds a padding field to a packet shorter than 64 bytes. note: setting this bit automatic ally enables add crc feature. 1 0 rw lmtac lan mac dma transmit add crc when set, the ksz8692mpb/KSZ8692XPB appends the crc to the end of the transmission frame. 0 0 rw lmte lan mac dma tx enable when the bit is set, the dma tx block is enabled and placed in a running state. when reset, the transmission process is placed in the stopped state after completing the transmission of the cu rrent frame. the stop transmission command is effective only when the transmission process is in the running state. 2.7.2 lan mac dma receive control register (lmdrxc offset 0x8004) the lan mac dma receive control register establishes the receive operating modes and commands for the lan port. this register should be one of the last scrs to be written as part of the receive initialization. the following table shows the register bit fields. bit field default value read/ write description 31:30 00 ro reserved 29:24 0x00 rw lmrbs lan dma receive burst size this field indicates the maximum number of words to be transferred in one dma transaction. if reset, the lan mac dma bur st size is limited only by the amound of data stored in the receive buffer bef ore issuing a bus request. the lmrbs can be programmed with permissible values 0,1, 2, 4, 8, 16, or 32. after reset, the lmrbs defaul t is 0, i.e. unlimited. 23:20 0x00 ro reserved 19 0 rw lihae lan ip header alignment enable when set, ksz8692mpb/KSZ8692XPB will align ip header at dword boundary if it?s an ip packet. 18 0 rw lmrucc lan mac receive udp checksum check when set, the ksz8692mpb/KSZ8692XPB will c heck for correct udp checksum for incoming udp/ip frames at lan port. packets received with incorrect udp checksum will be discarded.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 87 m9999-031810-1.2 17 0 rw lmrtcg lan mac receive tcp checksum check when set, the ksz8692mpb/KSZ8692XPB will c heck for correct tcp checksum for incoming tcp/ip frames at lan por t. packets received with incorrect tcp checksum will be discarded. 16 0 rw lmricg lan mac receive ip checksum check when set, the ksz8692mpb/ksz8692x pb will check for correct ip checksum for incoming ip frames at lan port.packets received with incorrect ip checksum will be discarded. 15 0 rw factory test only. must be left as default 0 14:11 0x00 ro reserved 10 0x0 rw ldlppdc lan drop low priority packet during congestion enable when this bit is set and the transmit flow control (bit9 of mac dma transmit control register) is disabled, the low priority packet will be dropped if the high watermark of low priority packet defined in lan mac rx watermark register is triggerred. ksz8692mpb/KSZ8692XPB will c ontinue dropping the low priority packet till the rx buffer is back to the low watermark state. the following table describes the action of ksz8692mpb/ KSZ8692XPB in the corresponding setting: transmit flow control enable drop low priority packet during congestion enable action 0 0 drop both hi and low priority packet when the hi watermark of low priority packet defined in mac rx watermark register is triggerred. 0 1 drop low priority packet when the hi watermark of low priority defined in mac rx watermark register is triggerred. drop both hi and low priority packet when the hi watermark of hi priority defined in mac rx watermark register is triggerred. 1 0 transmit flow control packet (or backpressure) when the hi watermark of low priority packet defined in mac rx watermark register is triggerred. 1 1 transmit flow control packet (or backpressure) when the hi watermark of low priority packet defined in mac rx watermark register is triggerred. note: the classification of the hi/low priority for each packet could be determined by diffserv, 802.1q or access control list rules.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 88 m9999-031810-1.2 9 0 rw lmrfce lan mac receive flow control enable when this bit is set and the ksz8692mpb/KSZ8692XPB is in full duplex mode, flow control is enabled and the ksz8692mpb/KSZ8692XPB will acknowledge a pause frame from the lan port, i.e., t he outgoing packets will be pending in the transmit buffer until the pause control timer expires. this field has no meaning in half-duplex mode and should be programmed to 0. when this bit is cleared, no flow control is enabled. 8:7 00 ro reserved 6 0 rw lmrb lan mac receive broadcast when set, the lan mac receive all broadcast frames. 5 0 rw lmrm lan mac receive multicast when set, the lan mac receive all mult icast frames (including broadcast). 4 0 rw lmru lan mac receive unicast when set, the lan mac receive unicast fr ames that match the 48-bit station address of the lan mac. 3 0 rw lmre lan mac dma receive error frame when set, the ksz8692mpb/KSZ8692XPB will pa ss the errors frames received to the host. error frames include runt frames, oversized frames, crc errors. 2 0 rw lmra lan mac dma receive all when set, the ksz8692mpb/KSZ8692XPB receives all incoming frames, regardless of its destination address. 1 0 rw lmche multicast hash filter enable when this bit is set, the multicas t hash filtering function is enabled . 0 0 rw lmre lan mac dma rx enable when the bit is set, the dma rx block is enabled and placed in a running state. when reset, the receive process is placed in the stopped state after completing the reception of the curr ent frame. the stop transmission command is effective only when the reception proce ss is in the running state. 2.7.3 lan mac dma transmit start command register (lmdtsc offset 0x8008) this register is written by the the cpu when pa ckets in the lan data buffer need to be transmitted. the following table shows the register bit fields. bit field default value read/ write description 31:0 0x0 wo ltsc lan transmit start command when written with any value, the lan transmit dma checks for frames to be transmitted. if no descriptor is availabl e, the transmit process returns to suspended state. if descriptiors are avail able, the transmit process starts or resumes. this bit is self-clearing.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 89 m9999-031810-1.2 2.7.4 lan mac dma receive start command register (lmdrsc offset 0x800c) this register is written by the the cpu when there are frame data in receive buffer to be processed. the following table shows the register bit fields. bit field default value read/ write description 31:0 0x0 wo lrsc lan receive start command when written with any value, the wlan receive dma checks for descriptors to be acquired. if no descriptor is availabl e, the receive process returns to suspended state and wait for the next receiv e restart command. if descriptiors are available, the receive process resu mes. this bit is self-clearing. 2.7.5 lan transmit descriptor list base address register (ltdlb offset 0x8010) this register is used for lan transmit descriptor list base address register. the register is used to point to the start of the appropriate descriptor list. writing to this register is permitted only when its respec tive process is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be word (32-bit) aligned. the ksz8692mpb/KSZ8692XPB behavior is unpredictable when the lists are not word-aligned. the following table shows the register bit fields. bit field default value read/ write description 31:2 0x0 rw lstl lan start of transmit list note: write can only occur when the transmit process stopped. 1:0 00 ro reserved 2.7.6 lan receive descriptor list base address register (lrdlb offset 0x8014) this register is used for lan receive descriptor list base address register. the register is used to point to the start of the appropriate descriptor list. writing to this register is permitted only when its respec tive process is in the stopped state. when stopped, the register must be written before the respective start command is given. note: the descriptor lists must be word (32-bit) aligned. the ksz8692mpb/KSZ8692XPB behavior is unpredictable when the lists are not word-aligned. the following table shows the register bit fields. bit field default value read/ write description 31:2 0x0 rw lsrl lan start of receive list note: write can only occur when the transmit process stopped. 1:0 00 ro reserved 2.7.7 lan mac station address low register (lmal offset 0x8018) station address is used to define the individual destination address the ksz8692mpb/KSZ8692XPB lan port will respond to when receiving frames. network addresses are gener ally expressed in the form of 01:23:45:67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 90 m9999-031810-1.2 the following table shows the register bit fields. bit field default value read/ write description 31:0 0x0 rw lmal lan mac station address low 4 bytes the least significant word of the lan mac station address. 2.7.8 lan mac station address high register (lmah offset 0x801c) station address is used to define the individual destination address the ksz8692mpb/KSZ8692XPB lan port will respond to when receiving frames. network addresses are gener ally expressed in the form of 01:23:45:67:89:ab, where the bytes are received left to right, and the bits within each byte are received right to left (lsb to msb). the actual transmitted and received bits are in the order of 10000000 11000100 10100010 11100110 10010001 11010101. the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 15:0 0x0 rw lmal lan mac station address high 2 bytes the most significant word of the lan mac station address. 2.7.9 lan mac misc. control register (lemc offset 0x8020) the ksz8692mpb/KSZ8692XPB port 1 support 10/100 mbps ethernet speed and some configuration modes are shown in the following table bit field default value read/ write description 31:16 0x0 ro reserved 15 0x1 rw factory reserved 14 0x1 rw factory reserved 13 0x0 rw factory test only. must be left as default 0 12 0x0 rw mac/phy mii mode select 0: mac mii mode 1: phy mii mode 11 0x0 rw mode select 1: factory reserved 0: mii mode is select (default) 10 0x0 rw jumbo frame support enable when set, the 9kb jumbo frame support is enabled. when cleared, the 9kb jumbo frame support is disabled. note: the 9kb jumbo frame is only supported at lan port. wan port can only supports up to 2000-byte packet size. 9 0x0 rw frame length check 8 0x1 rw excessive defer enable 7 0x1 rw receive enable 6 0x0 rw shortcut slot time counter 5 0x0 rw transmit half duplex flow control mode 2 enable 4 0x0 rw no excessive collision
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 91 m9999-031810-1.2 3 0x0 rw transmit collision limit 4 (super mac enable) when set, the ksz8692mpb/KSZ8692XPB collision back off algorithm will always limit the backoff timer to within 2^4 2:1 0x0 rw port 1 speed select 00: 10mbps 01: 100mbps 10: factory reserved 11: reserved 0 0x 0 rw duplex mode select 1: fullduplex mode, 0: half duplex mode. note: when ksz8692mpb/KSZ8692XPB is at 1gbps speed, only full-duplex mode is support. both the full-duplex and half -duplex modes are supported at 100/10 mbps speed. 2.7.10 factory reserved (lmipgl offset 0x 8068) 2.7.11 lan mac rx watermark register (lmwtr : offset 0x8028) the ksz8692mpb/KSZ8692XPB supports 24kb receive buffer size at lan port. the following table shows the register bit fields. bit field default value read/ write description 31:29 0x0 ro reserved 28:20 0x160 rw high watermark of high priority packet (22 k), 64 byte is the base unit 19 0x0 ro reserved 18:10 0x130 rw high watermark of low priority packet (19k), 64 byte is the base unit 9 0x0 ro reserved 8:0 0x80 rw low watermark(8 k), 64 byte is the base unit 2.7.12 lan mac multicast table low register (lmtrl: offset 0x802c) the 64 bit multicast table is used for group address filtering. the has value is defined as the six most significant bits of th e crc of the da. the most significant bits select the register to be used, while t he other determines the bit within the register. the following table shows the register bit fields. bit field default value read/ write description 31:0 0 rw lmtrl multicast table low when appropriate bit is set, the packet received with da matches the crc hashing function is receiv ed without being filtered. note: when the receive all (rxra) or rece ive multicast (rxrm) bit is set in the rxcr then all multicast addresses are rece ived regardless of t he multicast table value.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 92 m9999-031810-1.2 2.7.13 lan mac multicast table high register (lmtrh: offset 0x8030) the 64 bit multicast table is used for group address filtering. the has value is defined as the six most significant bits of th e crc of the da. the most significant bits select the register to be used, while the other determines the bit within the register. the following table shows the register bit fields. bit field default value read/ write description 31:0 0 rw lmtrh multicast table high when appropriate bit is set, the packet received with da matches the crc hashing function is receiv ed without being filtered. note: when the receive all (rxra) or rece ive multicast (rxrm) bit is set in the rxcr then all multicast addresses are rece ived regardless of t he multicast table value. 2.7.14 lan wakeup frame control register (lwfcr : offset 0x8034) this register holds control information programmed by the cpu to control the transmit module function. bit field default value read/ write description 15:8 0x00 ro reserved. 7 0 rw mprxe magic packet rx enable when set, it enables the magic packet pattern detection. when reset, the magic packet pattern detection is disabled. 6:4 0x0 ro reserved. 3 0 rw wf3e wake up frame 3 enable when set, it enables the wake up frame 3 pattern detection. when reset, the wake up frame pattern detection is disabled. 2 0 rw wf2e wake up frame 2 enable when set, it enables the wake up frame 2 pattern detection. when reset, the wake up frame pattern detection is disabled. 1 0 rw wf1e wake up frame 1 enable when set, it enables the wake up frame 1 pattern detection. when reset, the wake up frame pattern detection is disabled. 0 0 rw wf0e wake up frame 0 enable when set, it enables the wake up frame 0 pattern detection. when reset, the wake up frame pattern detection is disabled. 2.7.15 lan wakeup frame 0 crc register (lwf0crc: offset 0x8038) this register contains the expected crc va lues of the 1st wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw lwf0crc wake up frame 0 crc the expected crc value of a wake up frame 0 pattern.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 93 m9999-031810-1.2 2.7.16 lan wakeup frame 0 mask 0 register (lwf0mk0 : offset 0x803c) this register contains the first 32 byte mask values of the 1st wake up frame pattern. bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw lwf0bm0 wake up frame 0 mask 0 the first 32 byte mask of a wake up frame pattern. 2.7.17 lan wakeup frame 0 mask 1 register (lwf0mk1: offset 0x8040) this register contains the next 32 byte mask values of the 1st wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw lwf0bm1 wake up frame 0 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern. 2.7.18 lan wakeup frame 1 crc register (lwf1crc: offset 0x8044) this register contains the expected crc values of the 2nd wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw lwf1crc wake up frame 1 crc the expected crc value of a wake up frame 0 pattern. 2.7.19 lan wakeup frame 1 mask 0 register (lwf1mk0 : offset 0x8048) this register contains the first 32 byte mask values of the 2nd wake up frame pattern. bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw lwf1bm0 wake up frame 1 mask 0 the first 32 byte mask of a wake up frame pattern. 2.7.20 lan wakeup frame 1 mask 1 register (lwf1mk1: offset 0x804c) this register contains the next 32 byte mask values of the 2nd wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw lwf1bm1 wake up frame 1 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 94 m9999-031810-1.2 2.7.21 lan wakeup frame 2 crc register (lwf2crc: offset 0x8050) this register contains the expected crc va lues of the 3rd wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw lwf2crc wake up frame 2 crc the expected crc value of a wake up frame 0 pattern. 2.7.22 lan wakeup frame 2 mask 0 register (lwf2mk0 : offset 0x8054) this register contains the first 32 byte mask values of the 3rd wake up frame pattern . bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw lwf2bm0 wake up frame 2 mask 0 the first 32 byte mask of a wake up frame pattern. 2.7.23 lan wakeup frame 2 mask 1 register (lwf2mk1: offset 0x8058) this register contains the next 32 byte mask values of the 3rd wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw lwf2bm1 wake up frame 2 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern. 2.7.24 lan wakeup frame 3 crc register (lwf3crc: offset 0x805c) this register contains the expected crc va lues of the 4th wake up frame pattern. the value of the crc calculated is based on the ieee 802.3 et hernet standard, taken over t he bytes specified in the wake up byte mask registers. bit field default value read/ write description 31:0 -- rw lwf3crc wake up frame 3 crc the expected crc value of a wake up frame 0 pattern. 2.7.25 lan wakeup frame 3 mask 0 register (lwf3mk0 : offset 0x8060) this register contains the first 32 byte mask values of the 4th wake up frame pattern . bit 0 selects the first byte of the wake up frame, bit 31 selects the 32t th byte of the frame. bit field default value read/ write description 31:0 -- rw lwf3bm0 wake up frame 3 mask 0 the first 32 byte mask of a wake up frame pattern.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 95 m9999-031810-1.2 2.7.26 lan wakeup frame 3 mask 1 register (lwf3mk1: offset 0x8064) this register contains the next 32 byte mask values of the 4th wake up frame pattern. bit 0 selects the 33 th byte of the wake up frame, bit 31 selects the 64 nd byte of the frame. bit field default value read/ write description 31:0 -- rw lwf3bm1 wake up frame 3 mask 1 the next 32 byte mask covering bytes 32 to 64 of a wake up frame pattern. 2.7.27 lan broadcast traffic control register (lbtc 0x80e4) this register is used to regulate t he broadcast traffic which could possibly overwhelm the maximum cpu bandwidth in absorbing the ethernet traffic if no protecti on mechanism is provided. bit31 is the c ontrol bit to enable this function if it?s configured to 1. bit7-0 provides an 8-bit preload value to a decrement counter. when the incoming packet is a broadcast packet, the device will pass the packet if the current counter value is zero. if not zero, the broadcast packet will be dropped. no matter broadcast is passed or dr opped the counter is decremented by 1. t herefore, if the preload value is 1, half of the broadcast packets will be passed. if the preload val ue is 2, one third of the broadcast packets will be passed. the default setting is zero, which means device will accept all the broadcast traffic after power-on. the following table shows the bit fields of lbtc register. bit field default value read/ write description 31 0 rw lbtce lan broadcast traffic control enable: 1: enable 0: disable 30-8 0x0 ro reserved 7:0 0x0 rw lbtcplv lan broadcast traffic control preload value it?s value ranges from 0 to 255. 2.7.28 lan packet dropped count register (lpdc 0x80e8) this register is used to record the number of packet dropped due to the following reasons: 1. lan port receive buffer overrun 2. lan port acl filtering 3. lan port broadcast traffic control this register is cleared after read. the following table shows the bit fields of lpdc register. bit field default value read/ write description 31-0 0 rw lpdcv lan packet dropped count value 2.7.29 lan checksum error packet dropped count register (lcepdc: offset 0x80ec) this register is used to record the number of packet dropped due to the following reasons: 5. ip header checksum error 6. tcp checksum error 7. udp checksum error 8. icmp checksum error note: this counter is recommended for ipv4 systems only. this register is cleared after read. the following table shows the bit fields of lcepdc register.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 96 m9999-031810-1.2 bit field default value read/ write description 31-0 0 rw lcepdcv lan checksum error packet dropped count value 2.7.30 lan access control list 1 data register (lacl1d 0x8100) lan access control list 2 data register (lacl2d 0x8110) ? ? ? ? ? ? ? ? lan access control list 16 da ta register (lacl16d 0x81f0) lan access control list 17 data register (lacl17d 0x8104) lan access control list 18 data register (lacl18d 0x8114) ? ? ? ? ? ? ? ? lan access control list 32 da ta register (lacl32d 0x81f4) the acl function includes 32 acl data registers, 32 acl ma sk registers, and 32 acl confi guration registers to make up 32 rules for mac address (sa only), 32 rules or ipv4 header, and 8 rules for ipv6 header. for acl on mac address (sa only) or ipv4 header, each rule is made up of 1 acl data register, 1 acl mask register, and 1 acl configuration register. each rule can be pr ogrammed independently to support acl on mac or acl on ipv4 header. for acl on ipv6, these each rule is supported by a group made up of 4 consecutive-address data registers, 4 consecutive-address mask registers, and 4 consecutive-address configurat ion registers. each group can be programmed independently to support acl on ipv6 header. the lan access control list data register is used to configure the searched 32-bi t or part of 128-bit data pattern in the acl for mac address acl, 48-bit data pattern [47:0] = {lacl1m [15:0], lacl1d} for rule 1, ?, {lacl32m[15:0], lacl32d} for rule 32. no mask registers for mac address acl. for ipv4 rule, the 32-bit data pattern [31:0] = lacl1d for rule 1, ?, lacl32d for rule 32. for ipv6 rule, the 128-bit data pattern [127:0] = {lac l4d, lacl3d, lacl2d, lacl1d} for rule 1, ?, {lacl32d, lacl31d, lacl30d, lacl29d} for rule 8. the following table shows the bit fields of lacl1d register. bit field default value read/ write description 31-0 0 rw lacl1d lan access control list data pattern 2.7.31 lan access control list 1 mask register (lacl1m 0x8108) lan access control list 2 mask register (lacl2m 0x8118) ? ? ? ? ? ? ? ? lan access control list 16 mask register (lacl16m 0x81f8) lan access control list 17 mask register (lacl17m 0x810c) lan access control list 18 mask register (lacl18m 0x811c) ? ? ? ? ? ? ? ? lan access control list 32 mask register (lacl32m 0x81fc) this register is used to configure the mask value of the searched 32-bit or part of 128-bit data pattern in the access control list. for mac address acl, 48-bit data pattern [47:0] = {lacl1m [15:0], lacl1d} for rule 1, ?, {lacl32m[15:0], lacl32d} for rule 32. no mask registers for mac address acl. for ipv4 rule, the 32-bit data mask [31:0] = la cl1m for rule 1, ?, lacl32m for rule 32. for ipv6 rule, the 128-bit data mask [127:0] = {lacl4m , lacl3m, lacl2m, lacl1m} for rule 1, ?, {lacl32m, lacl31m, lacl30m, lacl29m} for rule 8.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 97 m9999-031810-1.2 the following table shows the bit fields of lacl1m register. bit field default value read/ write description 31-0 0 rw lacl1m lan access control list mask value 2.7.32 lan access control list 1 configuration register (lacl1c 0x8200) lan access control list 2 configuration register (lacl2c 0x8210) ? ? ? ? ? ? ? ? lan access control list 16 confi guration register (lacl16c 0x82f0) lan access control li st 17 configuration register (lacl17c 0x8204) lan access control li st 18 configuration register (lacl18c 0x8214) ? ? ? ? ? ? ? ? lan access control list 32 confi guration register (lacl32c 0x82f4) this register is used to c onfigure the access control list. for mac address acl, lacl1c is for ru le 1, ?, lacl32c is for rule 32. for ipv4 rule, lacl1c is for rule 1, ?, lacl32c is for rule 32. for ipv6 rule, lacl1c, lacl5c, lac l9c, lacl13c, lacl17c, lac l21c, lacl25c, lacl29c are used for rule 1, 2, 3, 4, 5, 6, 7 ,8 respectively. other la cl configuration registers are not used. the following table shows the bit fields of lacl1c register. bit field default value read/ write description 31 0 rw aclon when this bit is set, the access control list 1 is enabled. 30 0 rw ipv6s. this bit tells the acl is on ipv4 or ipv6. this bit is active only when macs = 0. when this bit is cleared, the systems is ip v4 systems, alc has 32 rules. each lacl configuration register can be programmed independently. when this bit is set, the systems is ipv6 systems, acl has 8 rules. note that this bit can only be set in registers lacl1c, lacl5c, lacl9c, lacl13c, lacl17c, lacl21c, lacl25c, lacl29c for rule 1, 2, 3, 4, 5, 6, 7 ,8 respectively for an ipv6 acl. for example, once the bit lacl1c[30] is set, then bit lacl2c[30], lacl3c[30], lacl4c[30] have no effect in order to avoid conflict on ipv6 rule 1; ?; once the bit lac l29c[30] is set, then bit lacl30c[30], lacl31c[30], lacl32c[30] have no effect in order to avoid conflict on ipv6 rule 8. 29 0 rw macs. this mac address is sa only. when this bit is cleared, the acl is for ipv4/ipv6 address. when this bit is set, the acl is for mac address. 28:20 0 ro reserved 19 0 rw flton. enable filter on the packet that matches the configured data pattern. 18:17 0 ro reserved 16 0 rw hipri when this bit is set, the pa cket that matches with the configured data pattern will be marked as high priority packet. 15 0 rw offsets when this bit is set, the o ffset address scheme is used for data match. the fstbt_ptr defined in bit5:0 is used as the first byte pointer. this is only valid when acl1on (bit31) is set.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 98 m9999-031810-1.2 14 0 rw ipv6sips when this bit is set, the 128-bit source ip address matching is enabled. this bit is valid only when the valid ipv6s (bit30) is set. note that this bit can only be progr ammed in registers lacl1c, lacl5c, lacl9c, lacl13c, lacl17c, lacl21c, lacl25c, lacl29c for rule 1, 2, 3, 4, 5, 6, 7 ,8 respectively for an ipv6 acl. for example, once the bit lacl1c[14] is programmed, then bit lacl2c[14], lacl3c [14], lacl4c[14] have no effect in order to avoid conflict on ipv6 rule 1; ?; once the bit lacl29c[14] is programmed, then bit lacl30c[14], lac l31c[14], lacl32c[14] have no effect in order to avoid conflict on ipv6 rule 8. 13 0 rw ipv6dips when this bit is set, t he 128-bit destination ip address matching is enabled. this bit is valid only when the valid ipv6s (bit30) is set. note that this bit can only be progr ammed in registers lacl1c, lacl5c, lacl9c, lacl13c, lacl17c, lacl21c, lacl25c, lacl29c for rule 1, 2, 3, 4, 5, 6, 7 ,8 respectively for an ipv6 acl. for example, once the bit lacl1c[13] is programmed, then bit lacl2c[13], lacl3c [13], lacl4c[13] have no effect in order to avoid conflict on ipv6 rule 1; ?; once the bit lacl29c[30] is programmed, then bit lacl30c[13], lac l31c[13], lacl32c[13] have no effect in order to avoid conflict on ipv6 rule 8. 12 0 rw procs when this bit is set, the 8-bit protocol field matching is enabled. once procs is on, the other select bits s hould be off and only the bit7-0 of data and mask registers are used. 11 0 rw spts when this bit is set, the 16-bit source port number matching is enabled. once spts is on, the other select bits should be off except dpts and only the bit15-0 of data and m ask registers are used. 10 0 rw dpts when this bit is set, the 16- bit destination port number matching is enabled. once dpts is on, the other select bi ts should be off except spts and only the bit15-0 of data and m ask registers are used. 9 0 rw ipv4sips when this bit is set, the 32-bit source ip address matching is enabled. once ipv4sips is on, the other select bi ts should be off except ipv4dips. this bit is valid only when ipv6s (bit30) is cleared. 8 0 rw ipv4dips when this bit is set, t he 32-bit destination ip address matching is enabled. once ipv4dips is on, the other select bits should be off except ipv4sips. this bit is valid onl y when ipv6s (bit30) is cleared. 7:6 0 ro reserved 5:0 0 rw fstbt_ptr this value indicates the fi rst byte location in the packet for the 32-bit data pattern maching. for instance, if the value is 0, the 1st/ 2nd/3rd/4th bytes of the packet will be used for comparision. if the value is 12, t he 13th/14th/ 15th/16th bytes of the packet will be used for comparision.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 99 m9999-031810-1.2 2.7.33 lan diff-serv priority control register 0 (ldspc0: offset 0x8300) the diff-serv priority control registers implement a fully decoded 64-bit dscp (differentiated service code point) to determine priority from the 6 bits of tos field in the ipv4/ip v6 header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that resu lts is compared against the corresponding bit in the dscp register. if the register bit is a 1, then priority is high; if it is a 0, the priority is low. the following table shows the bit fields of ldspc0 register. bit field default value read/ write description 31 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x1f 30 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x1e 29 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x1d 28 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x1c 27 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x1b 26 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x1a 25 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x19 24 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x18 23 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x17 22 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x16 21 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x15 20 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x14 19 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x13 18 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x12
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 100 m9999-031810-1.2 17 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x11 16 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x10 15 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x0f 14 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x0e 13 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x0d 12 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x0c 11 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x0b 10 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x0a 9 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x09 8 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x08 7 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x07 6 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x06 5 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x05 4 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x04 3 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x03 2 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x02 1 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x01 0 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x00
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 101 m9999-031810-1.2 2.7.34 lan diff-serv priority control register 1 (ldspc1: offset 0x8304) the diff-serv priority control registers implement a fully decoded 64-bit dscp (differentiated service code point) to determine priority from the 6 bits of tos field in the ipv4/ip v6 header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the singular code that resu lts is compared against the corresponding bit in the dscp register. if the register bit is a 1, the priority is high; if it is a 0, then priority is low. the following table shows the bit fields of ldspc1 register. bit field default value read/ write description 31 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x3f 30 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x3e 29 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x3d 28 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x3c 27 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x3b 26 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x3a 25 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x39 24 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x38 23 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x37 22 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x36 21 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x35 20 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x34 19 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x33 18 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame? s priority when the frame?s ip diffserv value is 0x32
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 102 m9999-031810-1.2 17 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x31 16 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x30 15 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2f 14 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2e 13 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2d 12 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2c 11 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2b 10 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x2a 9 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x29 8 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x28 7 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x27 6 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x26 5 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x25 4 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x24 3 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x23 2 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x22
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 103 m9999-031810-1.2 1 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x21 0 0 rw ipv4 and ipv6 mapping the value in this field is used as the frame?s priority when the frame?s ip diffserv value is 0x20 2.7.35 an diff-serv priority control register 2 (ldspc2: offset 0x8308) the following table shows the bit fields of ldspc2 register. bit field default value read/ write description 31:1 0x0 ro reserved 0 0 rw ip diff-serv priority enable when set, the priority of the incoming packet based on ip diffserv is active. when cleared, no priority decision is based on ip diffserv. 2.7.36 lan tag priority control register (ltpc: offset 0x830c) this register is used to map the 3-bit tag priority value of a frame to a defined priority. if the register bit is a 1, the pri ority is high; if it is a 0, the priority is low. the following table shows the bit fields of ltpc register. bit field default value read/ write description 31:9 0x0 ro reserved 8 0 rw ieee 802.1p enable when set, the priority of the incoming packet based on tag priority is active. when cleared, the tag priori ty function is disabled. 7 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x7 6 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x6 5 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x5 4 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x4 3 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x3 2 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x2 1 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x1
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 104 m9999-031810-1.2 0 0 rw ieee 802.1p mapping the value in this field is used as the frame?s priority when its ieee 802.1p tag has a value of 0x0 2.8 sdio registers (0xa000-0xafff) 2.8.1 sd host controller register map offset 15-08 bit 07-00 bit offset 15-08 bit 07-00 bit 002h system address(high) 000h system address (low) 006h block count 004h block size 00ah argument1 008h argument0 00eh command 00ch transfer mode 012h response1 010h response0 016h response3 014h response2 01ah response5 018h response4 01eh response7 01ch response6 022h buffer data port1 020h buffer data port 0 026h present state 024h present state 02ah walk-up control block gap control 028h power control host control 02eh software reset time-out control 02ch clock control 032h error interrupt status 030h normal interrupt status 036h error interrupt status enable 034h normal interrupt status enable 03ah error interrupt signal enable 038h normal interrupt signal enable 03eh --- 03ch auto cmd12 error status 042h capabilities 040h capabilities 046h capabilities (reserved) 044h capabilities (reserved) 04ah maximum current capabilities 048h maximum current capabilities 04eh maximum current capabilities (reserved) 04ch maximum current capabilities (reserved) --- --- --- ---
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 105 m9999-031810-1.2 0f2h --- 0f0h --- --- --- --- --- 0feh host controller version 0fch slot interrupt status
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 106 m9999-031810-1.2 2.8.2 classification of the standard register map
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 107 m9999-031810-1.2 2.8.3 configuration register types register attribute description ro read only register: register bits are r ead only and cannot be altered by software or any reset operation. write to these bits are ignored. roc read only status: these bits are initialized to zero at reset. writes to these bits are ignored. rw read-write register: register bits are read-write and may be either set or cleared by software to the desired state. rw1c read only status, write 1 to clear status: r egister bits indicate status when read, a set bit indicating a status event may be cleared by writ ing a 1. writing a 0 to rw1c bits has no effect. rwac read-write, automatic clear register: the host driver r equests a host controller operation by setting the bit. the host controller shall clear the bit automatically when the operation of complete. writing a 0 to rwac bits has no effect. hwinit hardware initialized: register bits are freezed. bits are read only after initialization, and writes to these bits are ignored. rsvd reserved: these bits are initialized to zero, and writes to them are ignored. 2.8.4 system address register (offset 000h) bit field default value read/ write description 31:0 0x0 rw dma system address this register contains the system me mory address for a dma transfer. when the host controller (hc) stops a dma transfer, this register shall point to the system address of the next contiguous data pos ition. it can be accessed only if no transaction is executing (i.e after a transaction has stopped). read operations during transfer return an invalid value. the host driver (hd) shall initialize this register before starti ng a dma transaction. after dma has stopped, the next system address of the next contiguous data position can be read from this register. the dma transfer waits at the every boundary specified by the host dma buffer size in the block size register . the host controller generates dma interrupt to request to update this register. the hd se t the next system address of the next data position to this register. when most upper byte of this register (003h) is written, the hc restart the dma transfer. when restarting dma by the resume command or by setting continue request in the block gap control register, the hc shall start at the next contiguous address stored here in the sy stem address register.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 108 m9999-031810-1.2 2.8.5 block count/size register (offset 004h) bit field default value read/ write description 31:16 0x0 rw blocks count for current transfer this register is enabled when block count enable in the transfer mode register is set to 1 and is valid only for multiple block transfers . the hc decrements the block count after each block transfer and stops when the count reac hes zero. it can be accessed only if no transaction is executing (i.e after a transac tion has stopped). read operations during transfer return an invalid value and write operations shall be ignored. when saving transfer context as a result of suspend command, the number of blocks yet to be transferred can be determined by reading this register. when restoring transfer context prior to issuing a resume command, the hd sha ll restore the previously save block count. 0000h - stop count 0001h - 1 block 0002h - 2 blocks --- --- ffffh - 65535 blocks 15 - - reserved 14:12 0x0 rw host dma buffer size to perform long dma transfer, system addre ss register shall be updat ed at every system boundary during dma transfer. these bits specify t he size of contiguous buffer in the system memory. the dma transfer shall wait at the every boundary specified by these fields and the hc generates the dma interrupt to request the hd to update the system address register. these bits shall support when the dma support in the capabilities register is set to 1 and this function is active when the dma enable in the transfer mode register is set to 1. 000b - 4kb(detects a11 carry out) 001b - 8kb(detects a11 carry out) 010b - 16kb(detects a11 carry out) 011b - 32kb(detects a11 carry out) 100b - 64kb(detects a11 carry out) 101b -128kb(detects a11 carry out) 110b - 256kb(detects a11 carry out) 111b - 512kb(detects a11 carry out) 11:0 0x0 rw transfer block size this register specifies the block size for bl ock data transfers for cmd17, cmd18, cmd24, cmd25, and cmd53. it can be accessed only if no transaction is executing (i.e after a transaction has stopped). read operat ions during transfer return an invalid value and write operations shall be ignored. 0000h - no data transfer 0001h - 1 byte 0002h - 2 bytes 0003h - 3 bytes 0004h - 4 bytes --- --- 01ffh - 511 bytes 0200h - 512 bytes --- --- 0800h - 2048 bytes
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 109 m9999-031810-1.2 2.8.6 argument register (offset 008h) bit field default value read/ write description 31:0 0x0 rw the sd command argument is specified as bit39-8 of command-format. 2.8.7 command/transfer mode register (offset 00ch) bit field default value read/ write description 31:30 - - reserved 29:24 0x0 rw command index this bit shall be set to the command number (cmd0-63, acmd0-63). 23:22 0x0 rw command type there are three types of special co mmands. suspend, resume and abort. these bits shall bet set to 00b for all other commands. suspend command if the suspend command succeeds, the hc shall assume the sd bus has been released and that it is possible to i ssue the next command which uses the dat line. the hc shall de-assert read wait for read transactions and stop checking busy for write transactions. the interrupt cycle shall start, in 4-bit mode. if the suspend command fails, the hc shall maintain its current state. and the hd shall restart the transfer by setting conti nue request in the block gap control register. resume command the hd re-starts the data transfer by rest oring the registers in the range of 000- 00dh. the hc shall check for busy before starting write transfers. abort command if this command is set when executing a r ead transfer, the hc shall stop reads to the buffer. if this command is set when ex ecuting a write transfer, the hc shall stop driving the dat line. after issui ng the abort command, the hd should issue a software reset 00b - normal 01b - suspend 10b - resume 11b ? abort 21 0x0 rw data present select this bit is set to 1 to indicate that data is present and sha ll be transferred using the dat line. if is set to 0 for the following: 1. commands using only cmd line (ex. cmd52) 2. commands with no data transfer but us ing busy signal on dat[0] line (r1b or r5b ex. cmd38) 3. resume command 0 - no data present 1 - data present 20 0x0 rw command index check enable if this bit is set to 1, the hc shall check the index field in the response to see if it has the same value as the command index . if it is not, it is reported as a command index error. if this bit is set to 0, the index field is not checked. 0 - disable 1 - enable
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 110 m9999-031810-1.2 19 0x0 rw command crc check enable if this bit is set to 1, the hc shall c heck the crc field in the response. if an erro r is detected, it is reported as a command crc error. if this bit is set to 0, the crc field is not checked. 0 - disable 1 - enable 18 - - reserved 17:16 0x0 rw response type select 00 - no response 01 - response length 136 10 - response length 48 11 - response length 48 check busy after response 15:6 0x0 - reserved 5 0x0 rw multi/single block select this bit enables multiple block dat line data transfers. 0 - single block 1 - multiple block 4 0x0 rw data transfer direction select this bit defines the directi on of dat line data transfers. 0 - write (host to card) 1 - read (card to host) 3 - - reserved 2 0x0 rw auto cmd12 enable multiple block transfers for memory r equire cmd12 to stop the transaction. when this bit is set to 1, the hc shall i ssue cmd12 automatically when last block transfer is completed. the hd shall not se t this bit to issue commands that do not require cmd12 to stop data transfer. 0 - disable 1 ? enable 1 0x0 rw block count enable this bit is used to enable the block count register, which is only relevant fo r multiple block transfers. when this bit is 0, the block count r egister is disabled, which is useful in executing an infinite transfer. 0 - disable 1 ? enable 0 0x0 rw dma enable dma can be enabled only if dma support bit in the capabilities register is set. i f this bit is set to 1, a dma operation shall begin when the hd writes to the uppe r byte of command register (00fh). 0 - disable 1 ? enable
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 111 m9999-031810-1.2 2.8.8 determination of transfer type multi / single block select block count enable block count function 0 don?t care don?t care single transfer 1 0 don?t care infinite transfer 1 1 not zero multiple transfer 1 1 zero stop multiple transfer 2.8.9 relation between parameters and the name of response type response type index check enable crc ch eck enable name of response type 00 0 0 no response 01 0 1 r2 10 0 0 r3, r4 10 1 1 r1, r6, r5 11 1 1 r1b, r5b 2.8.10 response register (offset 010h) bit field default value read/ write description 127:0 0x0 roc command response the following table describes the mappi ng of command responses from the sd bus to this register for each response type. in the table, r[] refers to a bit range within the response data as transmitted on t he sd bus, rep[] refers to a bit range within the response register. 2.8.11 response bit definition for each response type kind of response meaning of response response field response register r1, r1b (normal response) card status r[39: 8] rep[31:0] r1b (auto cmd12 response) card status for auto cmd12 r[39:8] rep[127:96] r2 (cid, csd register) cid or csd reg. incl. r[ 127:8] rep[119:0] r3 (ocr register) ocr register for memory r[39:8] rep[31:0] r4 (ocr register) ocr register for i/o etc. r[39:8] rep[31:0] r5, r5b sdio response r[39:8] rep[31:0] r6 (published rca response) new published rca[31:16] etc. r[39:8] rep[31:0]
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 112 m9999-031810-1.2 2.8.12 buffer data port register (offset 020h) bit field default value read/ write description 31:0 0x0 rw buffer data the host controller buffer can be acce ssed through this 32-bit data port register. 2.8.13 present state register (offset 024h) bit field default value read/ write description 31:25 0x0 - reserved 24 0x0 ro cmd line signal level this status is used to check cmd line level to recover from errors, and for debugging. 23:20 0x0 ro dat[3:0] line signal level this status is used to check dat line level to recover from errors, and for debugging. this is especially useful in detecting the busy signal level from dat[0]. d23 - dat[3] d22 - dat[2] d21 - dat[1] d20 - dat[0] 19 0x0 ro write protect switch pin level the write protect switch is supported for memory and combo cards. this bit reflects the sdwp# pin. 0 - write protected (sdwp# = 1) 1 - write enabled (sdwp# = 0) 18 0x0 ro card detect pin level this bit reflects the inverse value of the sdcd# pin. 0 - no card present (sdcd# = 1) 1 - card present (sdcd# = 0) 17 0x0 ro card state stable this bit is used for testing. if it is 0, the card detect pin level is not stable. if this bit is set to 1, it means the card dete ct pin level is stable. the software reset for all in the software reset regi ster shall not affect this bit. 0 - reset of debouncing 1 - no card or inserted 16 0x0 ro card inserted this bit indicates whether a card has been in serted. changing from 0 to 1 generates a card insertion interrupt in the normal interrupt st atus register and changing from 1 to 0 generates a card removal interrupt in the normal interrupt status register. the software reset for all in the software reset register shall not affect this bit. if a card is removed while its power is on and its clock is oscillating, the hc shall clear sd bus power in the power control register and sd clock enable in the clock control register. in addition the hd should clear the hc by the software reset for all in software register. the card detect is active regardless of the sd bus power. 0 - reset or debouncing or no card 1 - card inserted
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 113 m9999-031810-1.2 15:12 - - reserved 11 0x0 roc buffer read enable this status is used for non-dma read trans fers. this read only flag indicates that valid data exists in the host side buffer st atus. if this bit is 1, then readable data exists in the buffer. a change of this bit from 1 to 0 occurs when all the block data is read from the buffer. a change of this bi t from 0 to 1 occurs when all the block data is ready in the buffer and generates the buffer read ready interrupt. 0 - read disable 1 - read enable. 10 0x0 roc buffer write enable this status is used for non-dma write tr ansfers. this read only flag indicates if space is available for write data. if this bit is 1, then data can be written to the buffer. a change of this bit from 1 to 0 o ccurs when all the block data is written to the buffer. a change of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates the buffer write ready interrupt. 0 - write disable 1 - write enable 9 0x0 roc read transfer active this status is used for detecti ng completion of a read transfer. this bit is set to 1 for either of the following conditions: 1) after the end bit of the read command 2) when writing a 1 to continue request in the block gap control register to restart a read transfer this bit is cleared to 0 for either of the following conditions: 1) when the last data block as specified by block length is transferred to the system. 2) when all valid data blocks have been tr ansferred to the system and no current block transfers are being sent as a result of the stop at block gap request set to 1. a transfer complete interrupt is generated when this bit changes to 0. 1 - transferring data 0 - no valid data 8 0x0 roc write transfer active this status indicates a write transfer is ac tive. if this bit is 0, it means no valid write data exists in the hc. this bit is set in either of the following cases: 1) after the end bit of the write command. 2) when writing a 1 to continue request in the block gap control register to restart a write transfer. this bit is cleared in either of the following cases: 1) after getting the crc status of the last data block as specified by the transfer count (single or multiple) 2) after getting a crc status of any bl ock where data transmission is about to be stopped by a stop at block gap request. during a write transaction, a block gap ev ent interrupt is generated when this bit is changed to 0, as a result of the stop at block gap request being set. this status is useful for the hd in determi ning when to issue commands during write busy. 1 - transferring data 0 - no valid data 7:3 - - reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 114 m9999-031810-1.2 2 0x0 roc dat line active this bit indicates whether one of the dat line on sd bus is in use. 1 - dat line active 0 - dat line inactive 1 0x0 roc command inhibit (dat) this status bit is generated if either the dat line active or the read transfer active is set to 1. if this bit is 0, it indicates the hc can issue the next sd command. commands with busy signal belong to command inhibit (dat) (ex. r1b, r5b type). changing from 1 to 0 generates a transfer complete interrupt in the normal interrupt status register. note: the sd host driver can save registers in the range of 000-00dh for a suspend transaction after this bit has changed from 1 to 0. 1 - cannot issue command which uses the dat line 0 - can issue command which uses the dat line 0 0x0 roc command inhibit (cmd) if this bit is 0, it indicates the cmd li ne is not in use and the hc can issue a sd command using the cmd line. this bi t is set immediately after the command register (00fh) is written. this bit is cl eared when the command response is received. even if the command inhibit (d at) is set to 1, commands using only the cmd line can be issued if this bit is 0. changing from 1 to 0 generates a command complete interrupt in the normal interrupt status register. if the hc cannot issue the command because of a command conflict error or because of command not issued by auto cmd12 error, this bit shall remain 1 and the command complete is not set. status issu ing auto cmd12 is not read from this bit. this bit indicates whether one of the dat line on sd bus is in use. note : dat line active indicates whether one of the dat line is on sd bus is in use. a) in the case of read transactions this status indicates if a read transfer is executing on the sd bus. changes in th is value from 1 to 0 between data blocks generates a block gap event interrupt in the normal interrupt status register. this bit shall be set in either of the following cases: 1) after the end bit of the read command. 2) when writing a 1 to continue request in the block gap control register to restart a read transfer. this bit shall be cleared in either of the following cases: 1) when the end bit of the last data block is sent from the sd bus to the hc. 2) when writing a 1 to continue request in the block gap control register to restart a read transfer. this bit shall be cleared in either of the following cases: 1) when the end bit of the last data block is sent from the sd bus to the hc. 2) when beginning a wait read transfer at a stop at the block gap initiated by a stop at block gap request the hc shall wait at the next block gap by driving read wait at the start of the in terrupt cycle. if the read wait signal is already driven (data buffer cannot receiv e data),the hc can wait for current blo ck gap by continuing to drive the read wait signal. it is necessary to support read wait in order to use the suspend / resume function. b) in the case of write transactions this status indicates that a write tr ansfer is executing on the sd bus. c hanging this value from 1 to 0 generate a transfer complete interrupt in the normal interrupt status register. this bit shall be set in either of the following cases: 1) after the end of the write command. 2) when writing to 1 to continue request in the block gap control register to continue a write transfer. this bit shall be cleared in either of the following cases: 1) when the sd card releases write busy of the last data bl ock the hc shall also detect if output is not busy. if sd card does not drive busy signal for 8 sd clocks, the hc shall consider the card drive ?not busy?.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 115 m9999-031810-1.2 2) when the sd card releases write busy prior to waiting for write transfer as a result of a stop at block gap request . implementation note: the hd can issue cmd0, cmd12, cmd13 (for memory) and cmd52 (for sdio) when the dat lines are busy during data transfer. these commands can be issued when command inhibit (cmd) is set to zero. other commands shall be issued when command inhibit (dat) is set to zero. 2.8.14 wake-up, block gap, power and host control register (offset 028h) the wakeup register portion is mandatory for the hc, but the wakeup functionality depends upon the hc system hardware and software. the hd shall maintain voltage on the sd bus, by setting sd bus power to 1 in the power control portion of the register, when wakeup ev ent via card interrupt is desired. bit field default value read/ write description 31:27 - - reserved 26 0x0 rw wakeup even on sd card removal this bit enables wakeup event via card removal assertion in the normal interrup t status register. fn_wus (wake up support) in cis does not affect this bit. 1 - enable 0 - disable 25 0x0 rw wakeup event enable on sd card insertion this bit enables wakeup event via card insertion assertion in the normal interrupt status register. fn_wus (wake up support) in cis does not affect this bit. 1 - enable 0 - disable 24 0x0 rw wakeup event enable on card interrupt this bit enables wakeup event via card interrupt assertion in the normal interrupt status register. this bit can be set to 1 if fn_wus (wake up support) in cis is set to 1. 1 - enable 0 - disable 23:20 - - reserved 19 0x0 rw interrupt at block gap this bit is valid only in 4-bit mode of t he sdio card and selects a sample point in the interrupt cycle. setting to 1 enables interrupt detection at the block gap for a multiple block transfer. if the sd card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0. when the hd detects an sd card insertion, it shall set this bit a ccording to the cccr of the sdio card. 18 0x0 rw read wait control the read wait function is optional for sd io cards. if the card supports read wait, set this bit to enable use of the read wait protocol to stop r ead data using dat[2] line. otherwise the hc has to stop the sd clock to hold read data, which restricts commands generation. when the hd detects an sd card insertion, it shall set this bit according to the cccr of the sdio card. if the card does not support read wait, this bit shall never be set to 1 other wise dat line conflict may occur. if this bit is set to 0, suspend / resume cannot be supported 1 - enable read wait control 0 - disable read wait control
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 116 m9999-031810-1.2 17 0x0 rwac continue request this bit is used to restart a transacti on which was stopped using the stop at block gap request. to cancel stop at the blo ck gap, set stop at block gap request to 0 and set this bit to restart the transfer. the hc automatically clears this bit in either of the following cases: 1) in the case of a read transaction, the dat line active changes from 0 to 1 as a read transaction restarts. 2) in the case of a write transaction, t he write transfer active changes from 0 to 1 as the write transaction restarts. therefore it is not necessary for host driv er to set this bit to 0. if stop at block gap request is set to 1, any write to this bit is ignored. 1 - restart 0 - ignored 16 0x0 rw stop at block gap request this bit is used to stop executing a tr ansaction at the next block gap for both dma and non- dma transfers. until the transfer complete is set to 1, indicating a transfer completion the hd shall leave this bit set to 1. clearing both the stop at block gap request and continue request shall not cause the transaction to restart. read wait is used to stop the r ead transaction at the block gap. the hc shall honour stop at block gap request for write transfers, but for read transfers it requires that the sd card support r ead wait. therefore, the hd shall not set this bit during read transfers unless the sd card supports read wait and has set read wait control to 1. in case of writ e transfers in which the hd writes data to the buffer data port register, the hd shall set this bit after all block data is written. if this bit is set to 1, then hd shall not write data to buffer data port register. this bit affects read transfer active, writ e transfer active, dat line active and command inhibit (dat) in the present state register. 1 - stop 0 - transfer 15:12 - - reserved 11:9 0x0 rw sd bus voltage select by setting these bits, the hd selects the voltage level for the sd card. before setting this register, the hd shall c heck the voltage support bits in the capabilities register. if an unsupported voltage is select ed, then host system shall not supply sd bus voltage 111b - 3.3 v(typ.) 110b - 3.0 v(typ.) 101b - 1.8 v(typ.) 100b - 000b - reserved 8 0x0 rw sd bus power before setting this bit, the sd host driver shall set sd bus voltage select. if the hc detects the no card state, then this bit shall be cleared. 1 - power on 0 - power off 7:3 - - reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 117 m9999-031810-1.2 2 0x0 rw high speed enable this bit is optional. before setting this bit, the hd shall check the high speed support in the capabilities register. if this bit is set to 0 (default), then hc outputs cmd line and dat lines at the falling edge of the sd clock (up to 25 mhz). if this bit is set to 1, then hc outputs cmd li ne and dat lines at the rising edge of the sd clock (up to 50 mhz) 1 - high speed mode 0 - normal speed mode 1 0x0 rw data transfer width (sd1 or sd4) this bit selects the data widt h of the hc. the hd shall se lect it to match the data width of the sd card. 1 - 4 bit mode 0 - 1 bit mode 0 0x0 rw led control this bit is used to caution the user not to remove the card while the sd card is being accessed. if the software is going to issue multiple sd commands, then this bit can be set during all transactions. it is not necessary to change for each transaction. 1 - led on 0 - led off there are three cases to restart the transfer after stop at the block gap. which case is appropriate depends on whether the hc issues a suspend command or the sd card accepts the suspend command. 1) if the hd does not issue suspend command, the continue request shall be used to restart the transfer. 2) if the hd issues a suspend command and the sd card accepts it, a resume command shall be used to restart the transfer. 3) if the hd issues a suspend command and the sd card does not accept it, the continue request shall be used to restart the transfer. any time stop at block gap request stops the data transfer, the hd shall wait for transfer complete (in the normal interrupt status register) before attempting to restart the transfer. when restarting the data transfer by continue request , the hd shall clear stop at block gap request before or simultaneously. 2.8.15 software reset/time-out control/clock control register (offset 02ch) at the initialization of t he hc, the hd shall set the sdclk frequency select according to the capabilities register. at the initialization of t he hc, the hd shall set the data timeout counter value according to the capabilities register. bit field default value read/ write description 31:27 0x0 - reserved 26 0x0 rwac software reset for dat line only part of data circuit is re set. dma circuit is also reset. the following registers and bits are cleared by this bit: buffer data port register buffer is cleared and initialized. present state register buffer read enable buffer write enable read transfer active write transfer active dat line active
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 118 m9999-031810-1.2 command inhibit (dat) block gap control register continue request stop at block gap request normal interrupt status register buffer read ready buffer write ready block gap event transfer complete 1 - reset 0 - work 25 0x0 rwac software reset for cmd line only part of command circuit is reset. the following registers and bits are cleared by this bit: present state register command inhibit (cmd) normal interrupt status register command complete 1 - reset 0 - work 24 0x0 rwac software reset for all this reset affects the entire hc except for the card detection circuit. register bits of type roc, rw, rw1c, rwac are cleared to 0. during it s initialization, the hd shall set this bit to 1 to reset the hc. the hc shall reset this bit to 0 when capabilities registers are valid and the hd can read them. additional use of software rese t for all may not affect the value of the capabilities registers. if this bit is set to 1, then the sd card shall reset itself and must be reinitialized by the hd. 1 - reset 0 - work 23:20 0x0 - reserved 19:16 0x0 rw data timeout counter value this value determines the interval by which dat line timeouts are detected. refer to the data timeout error in the error interrupt status register for information on factors that dictate ti meout generation. timeout clock frequency will be generated by dividing the base clock tmclk by this value. when setting this register, prevent inadvertent timeout events by clearing the da ta timeout error status enable (in the error interrupt status enable register) 1111b - reserved 1110b - tmclk * 2^ 27 ------ - -------------------- 0001b - tmclk * 2^ 14 0000b - tmclk * 2^ 13
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 119 m9999-031810-1.2 15:8 0x0 rw sdclk frequency select this register is used to select the fr equency of the sdclk pin. the frequency is not programmed directly; rather this register holds the divisor of the base clock frequency for sd clock in the capabilities register. only the following settings are allowed. 80h - base clock divided by 256 40h - base clock divided by 128 20h - base clock divided by 64 10h - base clock divided by 32 08h - base clock divided by 16 04h - base clock divided by 8 02h - base clock divided by 4 01h - base clock divided by 2 00h - base clock(10mhz-63mhz) setting 00h specifies the highest frequency of the sd clock. when setting multiple bits, the most significant bit is used as the divisor. but multiple bits should not be set. the two default divider values can be calc ulated by the frequency that is defined by the base clock frequency for sd clock in the capabilities register. 1) 25 mhz divider value 2) 400 khz divider value the frequency of the sdclk is set by the following formula: clock frequency = (baseclock) / divisor . thus choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency. 7:3 - - reserved 2 0x0 rw sd clock enable the hc shall stop sdclk when writing this bit to 0. sdclk frequency select can be changed when this bit is 0. then, the hc shall maintain the same clock frequency until sdclk is stopped (stop at sdclk = 0). if the hc detects the no card state, this bit shall be cleared. 1 - enable 0 - disable 1 0x0 roc internal clock stable this bit is set to 1 when sd clock is stable after writing to internal clock enable in this register to 1. the sd host driver shall wa it to set sd clock enable until this bit is set to 1. note : this is useful when using pll for a clock oscillator that requires setup time. 1 - ready 0 - not ready 0 0x0 rw internal clock enable this bit is set to 0 when the hd is not us ing the hc or the hc awaits a wakeup event. the hc should stop its internal clock to go ve ry low power state. still, registers shall be able to be read and written. clock starts to oscillate when this bit is set to 1. when clock oscillation is stable, the hc shall set inte rnal clock stable in this register to 1. this bit shall not affect card detection. 1 - oscillate 0 - stop
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 120 m9999-031810-1.2 a reset pulse is generated when writing 1 to each bit of the so ftware reset portion of this register. after completing the reset, the hc shall clear each bit. because it takes some time to complete software reset, the sd host driver shall confirm that these bits are 0. 2.8.16 error interrupt status/normal interrupt status register (offset 030h) the normal interrupt status enable affects reads of the normal interupt status portion of this register, but normal interrupt signal does not affect these reads. an interrupt is generat ed when the normal interrupt signal enable is enabled and at least one of the status bits is set to 1. for all bits except card interrupt and error interrupt , writing 1 to a bit clears it. the card interrupt is cleared when the card stops asserting the inte rrupt: that is when the card driver services the interrupt condition. status defined in the error in terrupt status portion of this register can be enabled by the error interrupt status enable register , but not by the error interrupt signal enable register. the interrupt is generated when the error interrupt signal enable is enabled and at least one of the statuses is set to 1. writing to 1 clears the bit and writing to 0 keeps the bit unchanged. more than one status can be cl eared at the one register write. bit field default value read/ write description 31:29 0x0 rw1c vendor specific error status additional status bits can be defined in this register by the vendor. 28 0x0 rw1c target response error occurs when detecting error in m_hresp 0 - no error 1 - error 27:25 - - reserved 24 0x0 rw1c auto cmd12 error occurs when detecting that one of the bits in auto cmd12 error status register has changed from 0 to 1. this bit is set to 1 also when auto cmd12 is not executed due to the previous command error. 0 - no error 1 - error 23 0x0 rw1c current limit error by setting the sd bus power bit in the power control register, the hc is requested to supply power for the sd bus. if the hc s upports the current limit function, it can be protected from an illegal ca rd by stopping power supply to the card in which case this bit indicates a failure status. readi ng 1 means the hc is not supplying power to sd card due to some failure. reading 0 means that the hc is supplying power and no error has occurred. this bit shall always set to be 0, if the hc does not support this function. 0 - no error 1 - power fail 22 0x0 rw1c data end bit error occurs when detecting 0 at the end bit posit ion of read data whic h uses the dat line or the end bit positi on of the crc status. 0 - no error 1 - error 21 0x0 rw1c data crc error occurs when detecting crc error when trans ferring read data which uses the dat line or when detecting the wr ite crc status having a value of other than ?010?. 0 - no error 1 - error
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 121 m9999-031810-1.2 20 0x0 rw1c data timeout error occurs when detecting one of following timeout conditions. 1) busy timeout for r1b, r5b type 2) busy timeout after write crc status 3) write crc status timeout 4) read data timeout 0 - no error 1 - timeout 19 0x0 rw1c command index error occurs if a command index error occurs in the command response. 0 - no error 1 - error 18 0x0 rw1c command end bit error occurs when detecting that the end bit of a command response is 0. 0 - no error 1 - end bit error generated 17 0x0 rw1c command crc error command crc error is generated in two cases. 1) if a response is returned and the command timeout error is set to 0, this bit is set to 1 when detecting a crc error in the command response 2) the hc detects a cmd line conflict by monitoring the cmd line when a command is issued. if the hc drives the cmd line to 1 level, but detects 0 level on the cmd line at the next sdclk edge, t hen the hc shall abort the command (stop driving cmd line) and set this bit to 1. the command timeout error shall also be set to 1 to distinguish cmd line conflict. 0 - no error 1 - crc error generated 16 0x0 rw1c command timeout error occurs only if the no response is returned within 64 sdclk cycles from the end bit of the command. if the hc detects a cmd line conflict, in which case command crc error shall also be set. this bit shall be set without waiting for 64 sdclk cycles because the comm and will be aborted by the hc. 0 - no error 1 - timeout 15 0x0 roc error interrupt if any of the bits in the error interrupt status register are set, then this bit is set. therefore, the hd can test for an error by checking this bit first. 0 - no error. 1 - error. 14:9 - - reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 122 m9999-031810-1.2 8 0x0 roc card interrupt writing this bit to 1 does not clear this bit. it is cleared by resetting the sd card interrupt factor. in 1-bit mode, the hc shall detect the card interrupt without sd clock to support wakeup. in 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the card and the in terrupt to the host system. when this status has been set and the hd needs to start this interrupt service, card interrupt status enable in the normal interrupt status register shall be set to 0 inorder to clear the card interrupt statuses latched in the hc and stop driving the host system. after completion of the ca rd interrupt service (the reset factor in the sd card and the interrupt signal ma y not be asserted), set card interrupt status enable to 1 and start samp ling the interrupt signal again. 0 - no card interrupt 1 - generate card interrupt 7 0x0 rw1c card removal this status is set if the card inserted in the present state register changes from 1 to 0. when the hd writes this bit to 1 to clear this status the status of the card inserted in the present state register should be conf irmed. because the card detect may possibly be changed when the hd cl ear this bit an interrupt event may not be generated. 0 - card state stable or debouncing 1 - card removed 6 0x0 rw1c card insertion this status is set if the card inserted in the present state register changes from 0 to 1. when the hd writes this bit to 1 to clear this status the status of the card inserted in the present state register should be conf irmed. because the card detect may possibly be changed when the hd cl ear this bit an interrupt event may not be generated. 0 - card state stable or debouncing 1 - card inserted 5 0x0 rw1c buffer read ready this status is set if the buffe r read enable changes from 0 to 1. 0 - not ready to read buffer. 1 - ready to read buffer. 4 0x0 rw1c buffer write ready this status is set if the buffer write enable changes from 0 to 1. 0 - not ready to write buffer. 1 - ready to write buffer. 3 0x0 rw1c dma interrupt this status is set if the hc detects the host dma buffer boundary in the block size regiser. 0 - no dma interrupt 1 - dma interrupt is generated
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 123 m9999-031810-1.2 2 0x0 rw1c block gap event if the stop at block gap request in the block gap control register is set, this bit is set. read transaction : this bit is set at the falling edge of the dat line active status (when the transaction is stopped at sd bus timi ng. the read wait must be supported inorder to use this function). write transaction : this bit is set at the falling edge of writ e transfer active status ( after getting crc status at sd bus timing). 0 - no block gap event 1 - transaction stopped at block gap 1 0x0 rw1c transfer complete this bit is set when a read / write transaction is completed. read transaction : this bit is set at the falling edge of read transfer active status. there are two cases in which the interr upt is generated. the first is when a data transfer is completed as specified by data length (after the last data has been read to the host system). the second is when data has stopped at the block gap and completed the data transfer by setting the stop at block gap request in the block gap control register (after valid data has been read to the host system). write transaction : this bit is set at the falling edge of the dat line active status. there are two cases in which the interrupt is generated. the first is when the last data is written to the card as specified by data length and busy signal is released. the second is when data transfers are stopped at the block gap by setting stop at block gap request in the block gap control register and data transfers completed. (after valid data is written to the sd card and the busy signal is released). note : transfer complete has higher priori ty than data timeout error. if both bits are set to 1, the data transfer can be considered complete 0 - no data transfer complete 1 - data transfer complete 0 0x0 rw1c command complete this bit is set when get the end bit of the command response (except auto cmd12). note : command timeout error has higher priority than command complete. if both are set to 1, it can be consider ed that the response was not received correctly. 0 - no command complete 1 - command complete
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 124 m9999-031810-1.2 2.9 relation between transfer complete and data timeout error transfer complete data timeout error meaning of the status 0 0 interrupted by another factor. 0 1 timeout occur during transfer. 1 don?t care data transfer complete 2.10 relation between command complete and command timeout error transfer complete data timeout error meaning of the status 0 0 interrupted by another factor. don?t care 1 response not received within 64 sdclk cycles. 1 0 response received 2.11 relation between command crc error and command timeout error command crc error command time-out error kinds of error 0 0 interrupted by another factor. don?t care 1 response not received within 64 sdclk cycles. 1 0 response received 0 0 no error 0 1 response timeout error 1 0 response crc error 1 1 cmd line conflict
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 125 m9999-031810-1.2 2.12 error interrupt status enable/normal inte rrupt status enable register (offset 034h) bit field default value read/ write description 31:29 0x0 rw vendor specific error status enable 0 - masked 1 ? enabled 28 0x0 rw target response error status enable 0 - masked 1 ? enabled 27:25 0x0 - reserved 24 0x0 rw auto cmd12 error status enable 0 - masked 1 ? enabled 23 0x0 rw current limit error status enable 0 - masked 1 ? enabled 22 0x0 rw data end bit error status enable 0 - masked 1 ? enabled 21 0x0 rw data crc error status enable 0 - masked 1 ? enabled 20 0x0 rw data timeout error status enable 0 - masked 1 ? enabled 19 0x0 rw command index error status enable 0 - masked 1 ? enabled 18 0x0 rw command end bit error status enable 0 - masked 1 ? enabled 17 0x0 rw command crc error status enable 0 - masked 1 ? enabled 16 0x0 rw command timeout error status enable 0 - masked 1 ? enabled 15 0x0 ro fixed to 0 the hc shall control error interrupts using the error interrupt status enable register. 14:9 0x0 - reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 126 m9999-031810-1.2 8 0 x 0 rw card interrupt status enable if this bit is set to 0, the hc shall clear inte rrupt request to the system. the card interrupt detection is stopped when this bit is cleared and re started when this bit is set to 1. the hd should clear the card interrupt status enable before servicing the card interrupt and should set this bit again after all interrupt requests fr om the card are cleared to prevent inadvertent interrupts. 0 - masked 1 ? enabled 7 0x0 rw card removal status enable 0 - masked 1 ? enabled 6 0x0 rw card insertion status enable 0 - masked 1 ? enabled 5 0x0 rw buffer read ready status enable 0 - masked 1 ? enabled 4 0x0 rw buffer write ready status enable 0 - masked 1 ? enabled 3 0x0 rw dma interrupt status enable 0 - masked 1 ? enabled 2 0x0 rw block gap event status enable 0 - masked 1 ? enabled 1 0x0 rw transfer complete status enable 0 - masked 1 ? enabled 0 0x0 rw command complete status enable 0 - masked 1 ? enabled setting to 1 enables interrupt status. note: the hc may sample the card interrupt signal during inte rrupt period and may hold its value in the flip-flop. if the card interrupt status enable is set to 0, the hc shall clear all internal signals regarding card interrupt. note: to detect cmd line conflict, the hd must set both command time-out error status enable and command crc error status enable to 1. 2.12.1 error interrupt signal enable/normal interrupt signal enable register (offset 038h) this register is used to select which interrupt status is indica ted to the host system as the interrupt. these status bits all share the sample 1 bit interrupt line. setting any of these bits to 1 enables interrupt generation. bit field default value read/ write description 31:29 0x0 rw vendor specific error signal enable 0 - masked 1 ? enabled
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 127 m9999-031810-1.2 28 0x0 rw target response error signal enable 0 - masked 1 ? enabled 27:25 0x0 - reserved 24 0x0 rw auto cmd12 error signal enable 0 - masked 1 ? enabled 23 0x0 rw current limit error signal enable 0 - masked 1 ? enabled 22 0x0 rw data end bit error signal enable 0 - masked 1 ? enabled 21 0x0 rw data crc error signal enable 0 - masked 1 ? enabled 20 0x0 rw data timeout error signal enable 0 - masked 1 ? enabled 19 0x0 rw command index error signal enable 0 - masked 1 ? enabled 18 0x0 rw command end bit error signal enable 0 - masked 1 ? enabled 17 0x0 rw command crc error signal enable 0 - masked 1 ? enabled 16 0x0 rw command timeout error signal enable 0 - masked 1 ? enabled 15 0x0 ro fixed to 0 the hc shall control error interrupts using the error interrupt signal enable register. 14:9 0x0 - reserved 8 0x0 rw card interrupt signal enable 0 - masked 1 ? enabled 7 0x0 rw card removal signal enable 0 - masked 1 ? enabled 6 0x0 rw card insertion signal enable 0 - masked 1 ? enabled
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 128 m9999-031810-1.2 5 0x0 rw buffer read ready signal enable 0 - masked 1 ? enabled 4 0x0 rw buffer write ready signal enable 0 - masked 1 ? enabled 3 0x0 rw dma interrupt signal enable 0 - masked 1 ? enabled 2 0x0 rw block gap event signal enable 0 - masked 1 ? enabled 1 0x0 rw transfer complete signal enable 0 - masked 1 ? enabled 0 0x0 rw command complete signal enable 0 - masked 1 ? enabled the error interrupt signal enable portion of this register is used to select which interrupt st atus is notified to the host system as the interrupt. these status bits all share the same 1 bit interrupt li ne. setting any of these bits to 1 enables interrupt generation. 2.12.2 auto cmd12 error status register (offset 03ch) when auto cmd12 error status is set, the hd shall check th is register to identify what kind of error auto cmd12 indicated. this register is valid only when the auto cmd12 error is set. bit field default value read/ write description 31:8 0x0 - reserved 7 0x0 roc command not issued by auto cmd12 error setting this bit to 1 means cmd_wo_dat is not executed due to an auto cmd12 error (d04 - d01) in this register. 0 - no error 1 - not issued 6:5 0x0 - reserved 4 0x0 roc auto cmd12 index error occurs if the command index error occurs in response to a command. 0 - no error 1 - error 3 0x0 roc auto cmd12 end bit error occurs when detecting that the end bit of command response is 0. 0 - no error 1 - end bit error generated 2 0x0 roc auto cmd12 crc error occurs when detecting a crc error in the command response. 0 - no error 1 - crc error generated
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 129 m9999-031810-1.2 1 0x0 roc auto cmd12 timeout error occurs if the no response is returned within 64 sdclk cycles from the end bit of the command. if this bit is set to 1, the other error status bits (d04 - d02) are meaningless. 0 - no error 1 - timeout 0 0x0 roc auto cmd12 not executed if memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue auto cmd12. setting this bit to 1 means the hc cannot issue auto cmd12 to stop memory multiple block transfer due to some error. if this bit is set to 1, other error status bits (d04 - d01) are meaningless. 0 - executed 1 - not executed 2.13 relation between auto cmd12 crc error and auto cmd12 timeout error auto cmd12 crc error auto cmd12 timeout error kinds of error 0 0 no error 0 1 response timeout error 1 0 response crc error 1 1 cmd line conflict the timing of changing auto cmd12 error stat us can be classified in three scenarios: 1) when the hc is going to issue auto cmd12. set d00 to 1 if auto cmd12 cannot be issued due to an error in the previous command. set d00 to 0 if auto cmd12 is issued. 2) at the end bit of auto cmd12 response. check received responses by checking the error bits d01, d02, d03, d04. set to 1 if error is detected. set to 0 if error is not detected. 3) before reading the auto cmd12 error status bit d07 set d07 to 1 if there is a command cannot be issued. set d07 to 0 if there is no command to issue. timing of generating the auto cm d12 error and writing to the command register are asynchronous. then d07 shall be sampled when driver never writing to the command register. so, just before readi ng the auto cmd12 error status register, it is good timing to set the d07 status bit.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 130 m9999-031810-1.2 2.14 capabilities register (offset 040h) this register provides the hd with information specific to the hc implementation. the hc ma y implement these values as fixed or loaded from flash memory during power on initialization. bit field default value read/ write description 31:27 0x0 - reserved 26 0x1 hwinit voltage support 1.8v 0 - 1.8 v not supported 1 - 1.8 v supported 25 0x1 hwinit voltage support 3.0v 0 ? 3.0 v not supported 1 ? 3.0 v supported 24 0x1 hwinit voltage support 3.3v 0 - 3.3 v not supported 1 - 3.3 v supported 23 0x1 hwinit suspend/resume support this bit indicates whether the hc supports suspend / resume functionality. if this bit is 0, the suspend and resume mec hanism are not suppor ted and the hd shall not issue either suspend / resume commands. 0 - not supported 1 - supported 22 0x1 hwinit dma support this bit indicates whether the hc is capable of using dma to transfer data between system memory and the hc directly. 0 - dma not supported 1 - dma supported. 21 0x1 hwinit high speed support this bit indicates whether the hc and the host system support high speed mode and they can supply sd clock frequency from 25mhz to 50 mhz. 0 - high speed not supported 1 - high speed supported 20:18 0x1 hwinit reserved 17:16 0x1 hwinit max block length this value indicates the maximum block size that the hd can read and write to the buffer in the hc. the buffer shall transfe r this block size without wait cycles. three sizes can be defined as indicated below. 00 - 512 byte 01 - 1024 byte 10 - 2048 byte 11 ? reserved 15:14 0x0 - reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 131 m9999-031810-1.2 13:8 110000b hwinit base clock frequency for sd clock this value indicates the base (maximum) clock frequency for the sd clock. unit values are 1mhz. if the real frequency is 16.5 mhz, the larger value shall be set 010001b (17 mhz) because the hd uses this va lue to calculate the clock divider value and it shall not exceed the upper limit of the sd clock frequency. the supported range is 10mhz to 63 mhz. if these bits are all 0, the host system has to get information via another method. not 0 - 1 mhz to 63 mhz 000000b - get information via another method (registry entry). 7 0x1 hwinit timeout clock unit this bit shows the unit of base clo ck frequency used to detect data timeout error. 0 - khz 1 ? mhz 6 0x0 hwinit reserved 5:0 110000b hwinit timeout clock frequency this bit shows the base clock frequency used to detect data timeout error. not 0 - 1khz to 63khz or 1mhz to 63mhz 000000b - get information via another method. note: the host system shall support at least one of these voltages above. the hd sets the sd bus voltage select in power control register according to these support bits. if multiple voltages are supported, select the usable lower voltage by comparing the ocr value from the card. these registers indicate maximum current capabilit y for each voltage. the value is meaningful if voltage support is set in the capabilities register. 2.14.1 capabilities register (reserved) (offset 044h) bit field default value read/ write description 31:0 0x0 - reserved 2.14.2 maximum current capabilities register (offset 048h) bit field default value read/ write description 31:24 0x0 - reserved 23:16 0xff hwinit maximum current for 1.8v 15:8 0xff hwinit maximum current for 3.0v 7:0 0xff hwinit maximum current for 3.3v
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 132 m9999-031810-1.2 2.15 maximum current value definition table register value current value 0 get information via another method 1 4ma 2 8ma 3 12ma ------------------- ---------------------- 255 1020ma 2.15.1 maximum current capabilities (reserved) (offset 04ch) bit field default value read/ write description 31:0 0x0 - reserved 2.15.2 host controller version/slot interrupt status register (offset 0fch) bit field default value read/ write description 31:24 0x0 hwinit vendor version number this status is reserved for the vendor version number. the hd should not use this status. 23:16 0x0 hwinit specific ation version number this status indicates the host contro ller spec version. the upper and lower 4 bits indicate the version. 00 - sd host specification version 1.0 others - reserved 15:8 0x0 - reserved 7:0 0x0 roc interrupt signal for each slot these status bit indicate the logical or of interrupt signal and wakeup signal fo r each slot. a maximum of 8 slots c an be defined. if one interrupt signal is associated with multiple slots. the hd can know which interrupt is generated b y reading these status bits. by a power on re set or by software reset for all, the interrupt signal shall be deasserted and this status shall read 00h. bit 00 - slot 1 bit 01 - slot 2 bit 02 - slot 3 ----- ----- bit 07 - slot 8
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 133 m9999-031810-1.2 2.16 usb registers (0xb000-0xdfff) the ksz8692mpb/KSZ8692XPB includes two usb 2.0 controllers that can support both ehci or enhanced host controller and ohci or open host controller specifications. fo r more information on the ehci specification, please refer to usb 2.0 ehci host c ontroller specification, revision 1.0. for more information on the ohci, please refer to the usb 2.0 ohci host controller specification, rev.1.0a . the usb 2.0 host controller is designed with a usb 1.1 host controller interface at the port router, which allows the usb 2.0 host controller to communicate with high-, full- and low-speed devices connected at the utmi phy transceiver. the port router logic, which lies in t he ehci host controller and connects to t he ohci host controller, enables the host controllers to communicate with attached devices. the function of the port router logic is to route the attached device, depending on the device speed, to the ehci host controller or ohci host controller. as the ehci host controller is the default owner of each root port, when the a ttached device is not high-speed, the ehci host controller releases ownership of the port and control of the device to t he ohci host controller. otherwise, the ehci host controller retains ownership of the port and the data flow of that por t goes to the ehci host controller. t he ohci host controller can be integrated with the ehci host controller with no modification. 2.16.1 usb device configuration register (0xb000 ? 0xbfff) bit field default value read/ write description 31:20 - rw reserved 19 1?b0 rw ddr this bit indicates whether the ulpi phy data bus interface is in ddr (double data rate) or sdr (single data rate) mode. options are: - 1?b0: sdr mode. - 1?b1: ddr mode. note: this bit is reserved if the udc20-ahb subsystem is configured to support the utmi phy interface. this bit is also reserved for the udc11-ahb subsystem. 18 1?b0 rw set_desc indicates that the device s upports set descriptor requests. options are: - 1?b0: the udc-ahb subsystem returns a stall handshake to the usb host. - 1?b1: the setup packet for the se t descriptor request passes to the application. 17 1?b0 rw csr_prg the application can program the udc regi sters dynamically whenever it has received an interrupt for either a set c onfiguration or a set interface request. if this bit is enabled, the udc-ahb subsystem returns a nak handshake during the status in stage of bot h the set configuration and set interface requests until the application has written 1?b1 to the cs r_done bit 13 of the device control register. 16 1?b0 rw halt status this bit indicates whether the udc-ahb subystem must respond with a stall or an ack handshake when the usb host has issued a clear_feature (endpoint_halt) request for endpoint 0. options are: - 1?b0: ack - 1?b1: stall
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 134 m9999-031810-1.2 15:13 3?b000 rw hs_timeout calib these three bits indicate the number of phy clocks to the udc20-ahb subsystem?s timeout counter. the applicat ion uses these bits to increase the timeout value (736 to 848 bit times in high-speed operation), which depends on the phy?s delay in generating a line state condition. the default timeout value is 736 bit times. these bits are reserved for the udc11-ahb subsystem. 12:10 3?b000 rw fs_timeout calib these three bits indicate the number of phy clocks to the udc20-ahb subsystem?s timeout counter. the applicat ion uses these bits to increase the timeout value (16 to 18 bit times in full-speed operation), which depends upon the phy?s delay in generating a line state condition. the default timeout value is 16 bit times. these bits are reserved for the udc11-ahb subsystem. 9 1?b0 rw phy_error detect if the application sets this bit, the devic e detects the phy_rxva lid or phy_rxactive input signal to be continuously asserted fo r 2 ms, indicating phy error. this bit is reserved for the udc11-ahb subsystem. 8 - rw status_1 this bit, together with status bit 7, provides an option for the udc-ahb subsystem to respond to the usb host with a stall or ack handshake if the usb host has issued a non-zero-length data packet during the status-out stage of a control transfer. 7 - rw status this bit, together with status bit 8, provides an option for the udc-ahb subsystem to respond to the usb host with a stall or ack handshake if the usb host has issued a non-zero-length data packet during the status-out stage of a control transfer. 6 - rw dir this bit indicates if the utmi data bus interface has to support a unidirectional or bidirectional interface. options are: - 1?b0: unidirectional interface - 1?b1: bidirectional interface 5 - rw pi phy interface. indicates if the utmi phy must support an 8-bit or 16-bit interface. options are: - 1?b0: 16-bit - 1?b1: 8-bit 4 1?b0 rw ss indicates that the devic e supports sync frame 3 1?b0 rw sp indicates that the dev ice is self-powered 2 1?b0 rw rwkp indicates that the device is remote wake up capable. 1:0 2?b00 rw spd device speed. this is the expected speed the application programs to the subsystem. the actual speed t he subsystem operates depends on the enumeration speed (enum spd) of t he device status register. - 2?b00: hs (phy clock = 30 or 60 mhz) - 2?b01: fs (phy clock = 30 or 60 mhz) - 2?b10: ls (phy clock = 6 mhz) - 2?b11: fs (phy clock = 48 mhz) note: the udc11-ahb subsystem uses only bit 0; bit 1 is a ?don?t care? bit.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 135 m9999-031810-1.2 2.16.2 device control register this register is set at runtime and contro ls the device after device configuration. bit field default value read/ write description 31:24 8?d0 rw thlen threshold length indicates the number (thlen +1) of 32-bi t entries in the rxfifo before the dma can start data transfer. 23:16 8?d0 rw burst length indicates the length, in 32-bit transfe rs, of a single burst on the ahb. the subsystem sends number of 32-bit transfers equal to (brlen +1). 15:14 - - reserved 13 1?b0 w csr_done the application uses this bit to not ify the udc-ahb subsystem that the application has completed programming all required udc registers, and the subsystem can acknowledge the current set configuration or set interface command. 12 1?b0 rw devnak when the application sets this bit, the subsystem core returns a nak handshake to all out endpoints. by writing 1?b1 to this bit, the application does not need to write 1?b1 to the snak bit 7 of each endpoint control register. 11 1?b0 rw scale scale down this bit reduces the timer values inside the udc-ahb subsystem when running gate-level simulation only. when this bit is set to 1?b1, timer values are scaled down to reduce simulation time. reset this bit to 1?b0 for normal operation. 10 1?b0 rw sd soft disconnect the application software uses this bit to signal the udc20 to soft-disconnect. when set to 1?b1, this bit causes the device to enter the disconnected state. 9 1?b0 rw mode enables the application to dictate the subsystem?s operation in either dma mode (1?b1) or slave-only mode (1?b0) operation. 8 1?b0 rw bren burst enable when this bit is set, transfers on the ahb are split into bursts. 7 1?b0 rw the threshold enable when this bit is set, a number of quadlets equivalent to the threshold value is transferred from the rxfifo to the memory. 6 1?b0 rw bf the dma is in buffer fill mode and trans fers data into continguous locations pointed to by the buffer address. 5 1?b0 rw be system endianness bit a value of 1?b1 indicates a big endian system. 4 1?b0 rw du descriptor update when this bit is set, the dma updates t he descriptor at the end of each packet processed.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 136 m9999-031810-1.2 3 1?b0 rw tde transmit dma is enabled. 2 1?b0 rw rde receive dma is enabled. 1 - - reserved 0 1?b0 rw res resuming signaling on the usb to perform a remote wakeup resume, the app lication sets this bit to 1?b1. the udc-ahb subsystem signals the usb host to resume the usb bus; however, the application must first set rwkp bit 2 in the device configuration register (indicating that the subsystem supports the remote wakeup feature), and the usb host must already have issued a se t feature request to enable the device?s remote wakeup feature. 2.16.3 device status register this register reflects status information needed to servic e some of the interrupts. this is a read-only register. bit field default value read/ write description 31:18 14?h0000 ro ts frame number of the received sof for high-speed operation: ? [31:21]: millesecond frame number ? [20:18]: microframe number for full-speed operation: ? [31:29]: reserved ? [28:18]: millesecond frame number 17 - - reserved 16 1?b0 ro phy error either the phy_rxvalid or phy_rxactive input signal is detected to be continuously asserted for 2 ms, indicating phy error. the udc20-ahb subsystem goes to the suspend state as a result. when the application serves the early sus pend interrupt (es bit 2 of the device interrupt register) it also must check this bit to determine if the early suspend interrupt was generated due to phy error detection. this bit is reserved for the udc11-ahb subsystem. 15 1?b0 ro rxfifo empty rxfio emptiness ? 1?b1 rxfifo is empty ? 1?b0 rxfifo is not empty
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 137 m9999-031810-1.2 14:13 2?b00 ro enum spd enumerated speed. these bi ts hold the speed at which the subsystem comes up after the speed enumeration. ? if the expected speed (spd of the device configuration register) is high speed and the subsystem connects to a 1. 1 host controller, then after speed enumeration, these bits indicate that the subsystem is operating in full speed mode (2?b01 for spd ? 2b?00). * if the spd is high speed and the subsys tem connects to a 2.0 host controller, then after speed enumeration, these bits indicated that the subsystem is operating in high speed mode (2?b00 for spd = 2?b00). * if the speed is low speed or full speed and the subsystem connects to either a 1.1 or a 2.0 host controller, then after speed enumeration, t hese bits indicated that the subsystem is operating in low speed mode (2?b10 for spd = 2?b10) or full speed mode (2?b01 for spd = 2?b01, and 2?b11 for spd = 2?b11). possible options are: ? 2?b00 hs * 2?b01 fs ? 2?b10 ls ? 2?b11 fs note: these bits are used only for the udc20-ahb subsystem. 12 1?b0 ro susp suspend status. this bit is set as long as a suspend condition is detected on the usb. 11:8 4?b0000 ro alt this 4-bit field represents the alternat e setting to which the above interface is switched. 7:4 4?b0000 ro intf this 4-bit field reflects the inte rface set by the setinterface command 3:0 4?b0000 ro cfg this f-bit field reflects the configurat ion set by the setconfiguration command. 2.16.4 device interrupt register device interrupts are set when there are sy stem-level events. interrupt s are used by the applicati on to make system-level decisions. after checking the register, t he application must clear the interrupt by writing a 1?b1 to the correct bit. bit field default value read/ write description 31:7 - - reserved (31:6 in udcvci) 6 1?b0 r/wc enum speed enumeration is complete. note: this bit is only used for the udc20-ahb subystem. 5 1?b0 r/wc sof an sof token is detected on the usb. 4 1?b0 r/wc us a suspend is detected on the usb. note: for the udc20-ahb subsystem, t here is no suspend interrupt to the application if the phy clock is suspended via the suspendm signal.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 138 m9999-031810-1.2 3 1?b0 r/wc ur a reset is detected on the usb. note: if the application has not served th is interrupt, the udc subsystem returns a nak handshake for all transactions except the 8 setup packet bytes from the usb host. 2 1?b0 r/wc es an idle state has been detect ed on the usb for 3 milliseconds. 1 1?b0 r/wc si the device has received a set_interface command. note: if the application has not served this interrupt, the subsystem returns a nak handshake to all transactions except the 8 setup packet bytes coming from the usb host. 0 1?b0 r/wc sc the device has received a se t_configuration command. note: if the application has not served this interrupt, the subsystem returns a nak handshake to all transactions except the 8 setup packet bytes coming from the usb host. 2.16.5 device interrupt mask register the device interrupt mask can be set for system-level interrupts using this register. programming 1?b1 in the appropriate bit position in the interrupt mask register maks the designat ed interrupt. once masked, an interrupt signal will not reach the application, nor will its interrupt bit be set. bit field default value read/ write description 31:7 - - reserved (31:6 in udcvci) 6:0 1?b0 or 1?b1 r/wc mask mask equivalent device interrupt bit. 2.16.6 endpoint interrupt register the endpoint interrupt register is used to set endpoint-level interrupts. since all 16 endpoints can be bidirectional, each endpoint has two interrupt bits (one for each direction). the applic ation needs to clear the interrupt by writing a 1?b1 to the correct bit after checking the register. bit field default value read/ write description 31:16 1?b0 r/wc out ep one bit per out endpoint, set when t here is an event on that endpoint. 15:0 1?b0 r/wc in ep one bit per in endpoint, set when t here is an event on that endpoint.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 139 m9999-031810-1.2 2.16.7 endpoint interrupt mask register this register is used to mask endpoint interrupts. a write of 1?b1 to any bit of this register masks the corresponding endpoint for any possible interrupts. once masked, an interrupt signal does not reach the application nor will its interrupt bit be set. bit field default value read/ write description 31:16 1?b0 or 1?b1 rw out ep mask masks interrupts to the out endpoint equivalent to this value. 15:0 1?b0 or 1?b1 rw in ep mask masks interrupts to the in endpoint equivalent to this value. 2.16.8 endpoint-specific csrs 2.16.9 endpoint control register this register is used to program the endpoints as required by the application. if the endpoint is bi-directional, there will be two such endpoint registers. bit field default value read/ write description 31:12 - - reserved 11 1?b0 or 1?b1 rw close desc close descriptor channel for this endpoin t. this bit applies only to out endpoints and is available only when the close descriptor channel option is selected through coreconsultant. the application sets this bit to close the descriptor channel, and the udc subsystem clears this bit after the channel is closed. this bit provides the application with a mechanism to close the descriptors in cases where the usb host does not indicate an end-of-transfer (by issuing a short packet to the usb device). to close the descriptor channel for a particular endpoint, the application sets the close desc bit in the endpoint control register. when the channel is closed, the udc subsystem clears this bit and ggenerates an interrupt. this bit must be used only for bulk and interrupt out endpoints. in addition, before closing the descriptor, software mu st ensure that the current descriptor reachable by the dma is active (buffer st atus is host ready). when closed, the descriptor is marked with the last bit set. when the descriptor is closed, it is assigned one of the following descriptor statuses: ? buffer fill mode: accumulated byte count is available in the rx bytes field. ? packet-per-buffer with descriptor update mode: current reachable descriptor is marked with the last descriptor, and the rx bytes field is set to 0. ? packet-per-buffer without descriptor update mode: current reachable descriptor is marked with the last descriptor, and the accumulated byte count is available in the rx bytes field. when this bit is available, you can enable or disable it using the strap signal, ss_close_desc_ena_i. note: this bit is reserved for the udc11-ahb subsystem.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 140 m9999-031810-1.2 10 1?b0 rw send null send null packet this bit is available only when t he send null option is selected through coreconsultant. this bit provides the application with a mechanism to instruct the udc subsystem to send a null (zero-length) packet when no data is available in the particular endpoint?s txfifo. if this bet is set, w hen no data is available in the endpoint?s txfifo, the udc subsystem sends a null packet. when this bit is available, you can enabl e or disable it using the strap signal, ss_send_null_ena_i. note: this bit is reserved for the udc11-ahb subsystem. 9 1?b0 rw rrdy receive ready if this bit is set by the application, on receiving an out packet, the dma sends the packet to system memory. this bit is deasserted at the end of packet if the descriptor update bit is set in the device control register. this bit is deasserted at the end of payload if the de scriptor update is deasserted. this bit can be set by the application at any time. the application cannot clear this bit if the dma is busy transferring the data. if multiple receive fifo controllers is not implemented, this bit is reserved. 8 1?b0 wo cnak clear nak used by the application to clear the nak bi t (bit 6, below). after the subsystem sets bit 6 (nak), the application must clear it with a write of 1 to the cnak bit. (for example, after the applicat ion has decoded the setup packet and determined it is not an invalid command, t he application must set the cnak bit of the control endpoint to 1?b1 to clear the nak bit.) the application also must clear the nak bit whenever the subsystem sets it. (the subsystem sets it due to the app lication setting the stall bit.) the application can only clear this bit when the rxfifo is empty (for single rxfifo implementation) or when the rx fifo corresponding to the same logical endpoint is empty (multiple rxfifo implementation). 7 1?b0 wo snak set nak used by the application to set the nak bit (bit 6, below). the application must not set the nak bit for an in endpoint until it has received an in token interrupt indicating that the txfifo is empty. 6 1?b0 ro nak if set to 1, the endpoint responds to the usb host with a nak handshake. if set to 0, the endpoint responds normally. a setup packet is sent to the applicati on regardless of whether the nak bit is set. on successful reception of a setup packet (decoded by the application), the subsystem sets both the in and out nak bits for the control endpoint. the subsystem also sets this bit because of the stall bit set by the application. 5:4 2?b00 rw et endpoint type (2-bit) the possible options are: ? 2?b00: control endpoint ? 2?b01: isochronous endpoint ? 2?b10: bulk endpoint ? 2?b11: interrupt endpoint
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 141 m9999-031810-1.2 3 1?b0 rw p poll demand from the application. reserved for out endpoints. 2 1?bo rw sn configures the endpoint for snoop mode. in this mode, the subsystem does not check the correctness of out packets before transferring them to application memory. reserved for in endpoints. 1 1?b0 rw f flush the txfifo. reserved for out endpoints. 0 1?b0 rw stall handshake on successful reception of a setup packet (decoded by the application), the subsystem clears both in and out stall bits, and sets both the in and out nak bits. the application must check for rx fifo emptiness before setting the in and out stall bit. for non-setup packets, the subsystem clears ei ther in or out stall bits only if a stall handshake is returned to the usb host, then sets the corresponding nak bit. the subsystem returns a stall handshake for the subsequent transactions of the stalled endpoint unt il the usb host issues a clear_feature command to clear it. 2.16.10 endpoint status register the endpoint status register indicates the endpoint status. bit field default value read/ write description 31:24 - - reserved 23 1?b0 rw iso in done isochronous in transaction for the cu rrent microframe is complete. this bit indicates that the isochronous in transaction for this endpoint is complete. the application can use this information to program the isochronous in data fo r the next microframe. this bit is used only in slave-only mode. note: this bit is reserved for the udc11-ahb subsystem. 22:11 12?h0000 rw rx pkt size receive packet size indicates the number of bytes in the current receive packet the rxfifo is receiving. because the usb host always s ends 8 bytes of setup data, these bits do not indicate the receipt of 8 bytes of setup data for a setup packet. rather, these bits indicate the configuration status (configurat ion number [22:19], interface number [18:15], and alternate setti ng number [14:11]). this field is used in slave mode only. in dma mode, the application must c heck the status fr om the endpoint data descriptor. 10 1?b0 r/wc tdc transmit dma completion indicates the transmit dma has complet ed transferring a descriptor chain?s data to the tx fifo. after servicing the interr upt, the application must clear this bit. 9 1?b0 r/wc he error response on the host bus (ahb) when doing a data transfer, descriptor fetch, or descriptor update for this particu lar endpoint. after servicing the interrupt, the application must clear this bit.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 142 m9999-031810-1.2 8 - - reserved 7 1?b0 r/wc bna buffer not available the subsystem sets this bit when the descrip tor?s status is either host busy or dma done to indicate that the descriptor was not ready at the time the dma tried to access it. after servicing the interr upt, the application must clear this bit. 6 1?b0 r/wc in an in token has been received by this endpoi nt. after servicing the interrupt, the application must clear this bit. (reserved for out endpoints.) 5:4 2?b00 r/wc out an out packet has been received by this endpoint. the encoding of these two bits indicates the type of data rece ived. the possible options are: ? 2?b00: none ? 2?b01: received data ? 2?b10: received setup data (8 bytes) ? 2?b11: reserved 3:0 - - reserved 2.16.11 endpoint buffer size in/receive packet frame number out register this dual-function register holds the endpoint buffer size when the endpoint is an in endpoint. when the endpoint is an out endpoint, the register contains the frame number in whic h the packet is received, updated in bits 15:0. this frame number information is useful w hen handling isochronous traffic. bit field default value read/ write description 31:18 - - reserved 17:16 2?b00 rw iso in pid initial data pid to be sent for a hi gh-bandwidth isochronous in transaction this field is used only in slave-only mode. ? 2?b00: data0 pid is sent ? 2?b01: data0 pid is sent ? 2?b10: data1 pid is sent ? 2?b11: data2 pid is sent note: these bits are reserved for the udc11-ahb subsystem. 17:16 2?b00 ro iso out pid data pid received for a high-bandwidth isochronous out transaction. this field indicates that the data pid fo r the current packet is available in the receive fifo. this field is used only in slave-only mode. ? 2?b00: data0 pid is received ? 2?b01: data1 pid is received ? 2?b10: data2 pid is received ? 2?b11: mdata pid is received note: these bits are reserved for the udc11-ahb subsystem.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 143 m9999-031810-1.2 15:0 16?h0000 rw buff size buffer size required for this endpoint. the application can program this field to make each endpoint?s buffers adaptive, providing flexibility in buffer size when the interface or conf iguration is changed. this value is in 32-bit words, and indica tes the number of 32-bit word entries in the transmit fifo. (in only) 15:0 14?h0000 ro frame number frame number in which the packet is received. for high-speed operation: ? [15:14] reserved ? [13:3] millisec ond frame number ? [2:0] microframe number for full-speed operation: ? [15;11] reserved ? [10:0] millisec ond frame number 2.16.12 endpoint buffer size out/maximum packet size register this register holds the endpoint buffer size when the endpoint is an out endpoint. if multiple receive fifo controllers is not implemented, these buff size bits are reserved. this register also specifies the maximum packet size an endpoint should support. this maximum size is us ed to calculate whether the receive fi fo has sufficient space to accept a packet. when changing the maximum packet size for a specific endpoint, the user must also program the udc register space. bit field default value read/ write description 31:16 16?h0000 rw buff size buffer size required for this endpoint. the application can program this field to make each endpoint?s buffers adaptive, provid ing flexibility in buffer size when the interface or configuration is changed. this value is in 32-bit words, and indicates the number of 32-bit word entries in the receive fifo. if multiple receive fifo controllers is not implemented, these bits are reserved. 15:0 16?h0000 rw max pkt size maximum packet size for the endpoint. this is the value in bytes. 2.16.13 endpoint setup buffer pointer register endpoint setup buffer pointers are used for setup commands . the endpoint setup buffer register tracks control endpoint buffer registers: endpoint buffer registers for all ot her endpoint types are reserved. the endpoint setup buffer pointer register is used only in dma mode. this register is read- and write-capable, with a reset value of 32?h0000_0000. this is applicable only to control endpoints. for all other endpoints this is reserved. bit field default value read/ write description 31:0 32?h0000 rw subptr setup buffer pointer
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 144 m9999-031810-1.2 2.16.14 endpoint data descriptor pointer register this register contains data descriptor pointers. both in and out endpoints have one data descriptor pointer each. bit field default value read/ write description 31:0 32?h0000 rw desptr descriptor pointer 2.16.15 csr memory map the endpoint-specific csrs occupy the fi rst 512 bytes of the map. each endpoint consumes 32 bytes of memory space in both the in and out directions. all 16 endpoints are th us serviced by 512 bytes for each direction. the global csrs, which serve the device, consume 32 byte s of memory space. the following tabl e shows the address allocation for the csrs. csr offset address in endpoint-specific registers endpoint 0 control register 0x000 endpoint 0 status register 0x004 endpoint 0 buffer size register 0x008 endpoint 0 maximum packet size register 0x00c reserved 0x010 endpoint 0 data descriptor pointer register 0x014 reserved 0x018 endpoint 0 write confirmation regist er (for slave-only mode) 0x01c endpoint 1 registers 0x020 ? 0x03c endpoint 2 registers 0x040 ? 0x05c endpoint 3 registers 0x060 ? 0x07c endpoint 4 registers 0x080 ? 0x09c endpoint 5 registers 0x0a0 ? 0x0bc endpoint 6 registers 0x0c0 ? 0x0dc endpoint 7 registers 0x0e0 ? 0x0fc endpoint 8 registers 0x100 ? 0x11c endpoint 9 registers 0x120 ? 0x13c endpoint 10 registers 0x140 ? 0x15c endpoint 11 registers 0x160 ? 0x17c endpoint 12 registers 0x180 ? 0x19c endpoint 13 registers 0x1a0 ? 0x1bc endpoint 14 registers 0x1c0 ? 0x1dc endpoint 15 registers 0x1e0 ? 0x1fc out endpoint-specific registers endpoint 0 control register 0x200 endpoint 0 packet frame number register 0x208 endpoint 0 buffer size out/maximu m packet size register 0x20c endpoint 0 setup buffer pointer register 0x210 endpoint 0 data descriptor pointer register 0x214
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 145 m9999-031810-1.2 reserved 0x218 endpoint 0 read confirmation register for zero -length out data (for slave-only mode) 0x21c endpoint 1 registers 0x220 ? 0x23c endpoint 2 registers 0x240 ? 0x25c endpoint 3 registers 0x260 ? 0x27c endpoint 4 registers 0x280 ? 0x29c endpoint 5 registers 0x2a0 ? 0x2bc endpoint 6 registers 0x2c0 ? 0x2dc endpoint 7 registers 0x2e0 ? 0x2fc endpoint 8 registers 0x300 ? 0x31c endpoint 9 registers 0x320 ? 0x33c endpoint 10 registers 0x340 ? 0x35c endpoint 11 registers 0x360 ? 0x37c endpoint 12 registers 0x380 ? 0x39c endpoint 13 registers 0x3a0 ? 0x3bc endpoint 14 registers 0x3c0 ? 0x3dc endpoint 15 registers 0x3e0 ? 0x3fc global registers device configuration register 0x400 device control register 0x404 device status register 0x408 device interrupt register 0x40c device interrupt mask register 0x410 endpoint interrupt register 0x414 endpoint interrupt mask register 0x418 test mode register. reserved if te st mode is not supported. 0x41c reserved 0x420 ? 0x4fc udc registers 0x500 ?0x7fc apart from the subsystem csrs, the udc contains csrs that require 768 bytes of memory space. these csrs are mapped to the 500h-7fch address space. the setup command address pointer register (offset address 500h) is no longer writable and returns 0 when read, because the set up command address pointer is already hardcoded to 16?hfff0 in both the subsystem and the udc core. the applicat ion must use an offset address, starting from 504h, then 508h, and so on, to program the udc core?s endpoint buffers. t he subsystem maps these offset addresses in turn with the udc csr addresses, starting from 4h, 8h, and so on. writing to the offset address (offset 12?h01c + [endpoint number x 12?h020] (hexidecimal) confirms the in data into the txfifo. this is applicable only in the slave-only mode of operation. the data in the rxfifo is mapped from address 800h up to an address of the user?s design, which is followed by the address space of the txfifo.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 146 m9999-031810-1.2 memory map (from processor viewpoint)
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 147 m9999-031810-1.2 2.16.16 udcvci endpoint register bit field default value read/ write description 31:29 - - reserved 28:19 10?h000 rw maximum packet size 18:15 4?b0000 rw alternate setting to which this endpoint belongs. 14:11 4?b0000 rw interface number to which this endpoint belongs. 10:7 4?b0000 rw configuration number to which this endpoint belongs. 6:5 2?b00 rw endpoint type: the possible options are: ? 2?b00: control ? 2?b01: isochronous ? 2?b10: bulk ? 2?b11: interrupt 4 1?b0 rw endpoint direction. the possible options are: ? 1?b0: out ? 1?b1: in 3:0 4?b0000 rw logical endpoint number 2.16.17 udc20 endpoint register bit field default value read/ write description 31:30 - - reserved 29:19 11?h000 rw maximum packet size 18:15 4?b0000 rw alternate setting to which this endpoint belongs. 14:11 4?b0000 rw interface number to which this endpoint belongs. 10:7 4?b0000 rw configuration number to which this endpoint belongs. 6:5 2?b00 rw endpoint type: the possible options are: ? 2?b00: control ? 2?b01: isochronous ? 2?b10: bulk ? 2?b11: interrupt 4 1?b0 rw endpoint direction. the possible options are: ? 1?b0: out ? 1?b1: in 3:0 4?b0000 rw logical endpoint number
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 148 m9999-031810-1.2 2.16.18 ehci capability and operational registers (0xc000 ? 0xcfff) the ehci capability and operational registers are stored in this block of memory. 2.17 capability registers mnemonic register name offset from ehci ahb slave start address default value hccapbase capability register fields include: caplength 1 (8 bits) reserved (8 bits) hciversion 2 (16 bits) usbbase + 00h usbbase + 00h usbbase + 01h usbbase + 02h 32?h01000010 hcsparams structural parameter usbbase + 04h 32?h00001116 hccparams capability parameter usbbase + 08h 32?h0000a010 note: the isochronous scheduling threshold value is set to 1 by default. if descriptor/data prefetch is selected, the value is set 2. hcsp-portroute companion port route description usbbase + 0ch - 1 caplength ? capability registers length is read only. this regist er is used as an offset to add to register base to find the beginning of the operational register space. 2 hciversion ? host controller interface version number is read only with default value of 0100h. his is a two-byte register co ntaining a bcd encoding of the ehci revision number supported by this hostcontroller. the most signific ant byte of this register represents a major revision and the least significant byte is the minor revision. 2.18 operational registers mnemonic register name offset from ehci ahb slave start address 1 default value usbcmd usb command usbopbase + 00h 32?h00080000 or 32?h00080b00 2 usbsts usb status usbopbase + 04h 32?h00001000 usbintr usb interrupt enable usbopbase + 08h 32?h00000000 frindex usb frame index usbopbase + 0ch 32?h00000000 ctrldssegment 4g segment selector usbopbase + 10h 32?h00000000 periodiclistbase periodic frame list base address register usbopbase + 14h 32?h00000000 asynclistaddr asynchronous list address usbopbase + 18h 32?h00000000 configflag configured flag register usbopbase + 40h 32?h00000000 portsc_1 to portsc_15 port status/control usbopbase + 44h 32?h00002000 1 usbbase is fixed to the ehci slave start address (offset = 'h0) and usbo pbase is fixed to the ehci slave start address + `h10 (offset = `h10). 2 the default value depends on whether async park capability is enabled. disabled = 32'h0008_0000 and enabled = 32'h0008_0b00. the default value is 32'h0008_0000 if async park capability is disabled. it is 32'h0008_0b00 if async park capability is enabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 149 m9999-031810-1.2 2.18.1 echi capability register ? hcsparams (usbbase + 0x04) bit field read/ write description 31:24 rw reserved. these bits are reserved and should be set to zero. 23:20 rw debug port number. optional. this register identifies which of the host controller ports is the debug port. the value is the port number (one-based) of the debug port. a nonzero value in this field indicates the presence of a debug port. the value in this register must not be greater t han n_ports (see below). 19:17 rw reserved. these bits are reserved and should be set to zero. 16 rw port indicators (p_indicator). this bit indicates whether the ports support port indicator control. when this bit is a one, the port status and cont rol registers include a read/writeable field for controlli ng the state of the port indica tor. see section 2.3.9 for definition of the port i ndicator control field. 15:12 rw number of companion controller (n_cc). this field indicates the number of companion controllers associated with this usb 2.0 host controller. a zero in this field indicates there are no companion host controllers. port-ownership hand-off is not supported. only high-speed dev ices are supported on the host controller root ports. a value larger than zero in this field indicates there are companion usb 1.1 host controller(s). port-ownership hand-offs are supported. high, full- and low-speed devices are supported on the host controller root ports. 11:8 rw number of ports per companion controller (n_pcc). this field indicates the number of ports supported per companion host controller. it is used to indicate the port routing configuration to system software. for example, if n_ports has a value of 6 and n_cc has a value of 2 then n_pcc could have a value of 3. the convention is t hat the first n_pcc ports are assumed to be routed to companion controller 1, the next n_ pcc ports to companion controller 2, etc. in the previous example, t he n_pcc could have been 4, wher e the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2. the number in this field must be consistent with n_ports and n_cc. 7 rw port routing rules. this field indicates the method used by this implementation for how all ports are mapped to companion contro llers. the value of this field has the following interpretation: value meaning 0 the first n_pcc ports are routed to the lowest numbered function companion host controller, the next n_p cc port are routed to the next lowest function companion controller, and so on. 1 the port rout ing is explicitly enumerated by the first n_ports elements of the hcsp-portroute array.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 150 m9999-031810-1.2 6:5 rw port power control (ppc). this field indicates whether the host controller implementation includes port pow er control. a one in this bit indicates the ports have port power switches. a zero in this bit indicates the port do not have port power switches. the value of this field affects the functionality of the port power field in each port status and control register (see se ction 2.3.8 of echi specification). 3:0 rw n_ports. this field specifies the number of physical downstream ports implemented on this host controller. the value of this field determines how many port registers are addressable in the operational register space. valid values are in the range of 1h to fh. a zero in this field is undefined. 2.18.2 echi capability register ? hccparms (usbbase + 0x08) bit field read/ write description 31:16 rw reserved 15:8 rw ehci extended capabilities pointer (eecp). default = implementation dependent. this optional field indicates the existence of a capabilities list. a value of 00h indicates no extended capabilities are implem ented. a non-zero value in this register indicates the offset in pci configuration space of the fi rst ehci extended capability. the pointer value must be 40h or greater if implemented to ma intain the consistency of the pci header defined for this class of device. 7:4 rw isochronous scheduling threshold. default = implementation dependent. this field indicate s, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. when bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the stat e. when bit [7] is a one, then host software assumes the host controller may ca che an isochronous data st ructure for an entire frame. refer to section 4.7.2.1 in the echi specification for det ails on how software uses this information for scheduling isochronous transfers. 3 rw reserved. this bit is reserved and should be set to zero. 2 rw asynchronous schedule park capability. default = implementation dependent. if this bit is se t to a one, then the host controller supports the park feature for high-speed queue heads in the asynchronous sc hedule. the feature can be disabled or enabled and set to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park mode count fields in the usbcmd register. 1 rw programmable frame list flag. default = implementation dependent. if this bit is set to a zero, then system software must use a fr ame list length of 1024 elements with this host controller. the usbcmd register frame list size field is a read-only register and should be set to zero. if set to a one, then system software can specif y and use a smaller frame list and configure the host controller via the usbcmd register frame list size field. the frame list must always be aligned on a 4k page boundary. this requirement ensures that the frame list is always physically contiguous.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 151 m9999-031810-1.2 0 rw 64-bit addressing capability1. this field documents the addressing range capability of this implementat ion. the value of this field determines whether software should use the data structures defined in section 3 (32-bit) or those defined in appendix b (64-bit). values for this field have the following interpretation: 0b data structures using 32-bit address memory pointers 1b data structures using 64-bit address memory pointers [1] this is not tightly coupled with the usbbase address register mapping control. the 64-bit addressing capability bit indicates whether the host controller can generate 64-bit addr esses as a master. the usbbase register indicates the host controller only needs to decode 32-bit addresses as a slave. 2.18.3 ehci operational register ? usbcmd (usbopbase + 0x00) bit field read/ write description 31:24 rw reserved. these bits are reserved and should be set to zero. 23:16 rw interrupt threshold control default 08h. this field is used by system softwar e to select the maximum rate at which the host controller will issue interrupts. the only valid val ues are defined below. if software writes an invalid value to this register, the results are undefined. value maximum interrupt interval 00h reserved 01h 1 micro-frame 02h 2 micro-frames 04h 4 micro-frames 08h 8 micro-frames (default, equates to 1 ms) 10h 16 micro-frames (2 ms) 20h 32 micro-frames (4 ms) 40h 64 micro-frames (8 ms) refer to section 4.15 for interrupts affected by this register. any other value in this register yields undefined results. software modifications to this bit while hchalted bit is equal to zero results in undefined behavior. 15:12 rw reserved. these bits are reserved and should be set to zero. 11 ro or rw asynchronous schedule park mode enable (optional) if the asynchronous park capability bit in the hccparams register is a one, then this bit defaults to a 1h and is r/w. otherwise the bit must be a ze ro and is ro. software uses this bit to enable or disable park mode. when this bit is one, park mode is enabled. when this bit is a zero, park mode is disabled. 10 rw reserved. these bits are reserved and should be set to zero. 9:8 ro or rw asynchronous schedule park mode count (optional) if the asynchronous park capability bit in the hccparams register is a one, then this field defaults to 3h and is r/w. otherwise it defaults to zero and is ro. it contains a count of the number of successive transactions the host contro ller is allowed to execute from a high-speed queue head on the asynchronous schedul e before continuing traver sal of the asynchronous schedule. see section 4.10. 3.2 of echi specification for full operational details. valid values are 1h to 3h. software must not write a zero to this bit when park mode enable is a one as this will result in undefined behavior.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 152 m9999-031810-1.2 7 rw light host controller reset (optional) this control bit is not required. if implemented, it allows the driv er to reset the ehci controller without affecting the state of t he ports or the relationship to the companion host controllers. for example, the porstc registers should not be reset to their default values and the cf bit setting should not go to zero (retaining port ownership relationships). a host software read of this bit as zero indicate s the light host controller reset has completed and it is safe for host software to re-initialize the host controller. a host software read of this bit as a one indicates the light host contro ller reset has not yet completed. if not implemented a read of this field will always return a zero. 6 rw interrupt on async advance doorbell this bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. software must write a 1 to this bit to ring the doorbell. when the host controller has ev icted all appropriate cached sc hedule state, it sets the interrupt on async advance status bit in the usbsts register. if the interrupt on async advance enable bit in the usbintr register is a one then the host controller will assert an interrupt at the next interrupt threshold. see section 4.8.2 of echi specification for operational details. the host controller sets this bit to a zero after it has set the interrupt on async advance status bit in the usbsts register to a one. software should not write a one to this bit when the asynchronous schedule is disabled. doing so will yield undefined results. 5 rw asynchronous schedule enable default 0b. this bit controls whether the hos t controller skips processing the asynchronous schedule. values mean: 0b do not process the asynchronous schedule 1b use the asynclistaddr register to access the asynchronous schedule. 4 rw periodic schedule enable default 0b. this bit controls whether the host controller skips processing the periodic schedule. values mean: 0b do not process the periodic schedule 1b use the periodiclistbase register to access the periodic schedule. 3:2 rw or ro frame list size default 00b. this field is r/w only if programmable frame list flag in the hccparams registers is set to a one. this field specifies the size of the frame list. the size the frame list controls which bits in the frame index register should be used for the frame list current index. values mean: 00b 1024 elements (4096 bytes) default value 01b 512 elements (2048 bytes) 10b 256 elements (1024 bytes) ? for resource-constrained environments 11b reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 153 m9999-031810-1.2 1 rw host controller reset (hcreset) this control bit is used by software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset. when software writes a one to this bit, the host c ontroller resets its inte rnal pipelines, timers, counters, state machines, etc. to their initial value. any transacti on currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. pci configuration registers are not affected by this reset. all operational registers, including port registers and port state machines are set to their initial values. port ownership reverts to the companion host controller(s), with the side effe cts described in section 4.2 fo the echi specification. software must rein itialize the host controller as descr ibed in section 4.1 in the echi specification in order to return the host controller to an operational state. this bit is set to zero by the host c ontroller when the reset process is complete. software cannot terminate the reset process early by writing a zero to this register. software should not set this bit to a one when the hchalted bit in the usbsts register is a zero. attempting to reset an actively running host controller will result in undefined behavior. 0 rw run/stop (rs) default 0b. 1=run. 0=stop. when se t to a 1, the host controller proceeds with execution of the schedule. the host controller continues execution as long as this bit is set to a 1. when this bit is set to 0, the host controller completes the cu rrent and any actively pipelined transactions on the usb and then halts. the hostcontroller must halt wi thin 16 micro-frames after software clears the run bit. the hc halted bit in the status register indicates when the host controller has finished its pending pipelined transactions and has entered the stopped st ate. software must not write a one to this field unless the host contro ller is in the halted state (i.e. hchalted in the usbsts registe r is a one). doing so will yield undefined results. 2.18.4 ehci operational register ? usbsts (usbopbase 0x04) bit field read/ write description 31:16 rw reserved. these bits are reserved and should be set to zero. 15 rw asynchronous schedule status 0=default. the bit reports the current real status of the asynchronous schedule. if this bit is a zero then the status of the as ynchronous schedule is disabled. if this bit is a one then t he status of the asynchronous schedule is enabled. the host controller is not required to immediately disable or enable the asynchronous schedule when software tr ansitions the asynchronous schedule enable bit in the usbcmd register. when this bit and the asynchronous schedule enable bit are the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 rw periodic schedule status 0=default. the bit reports the current real status of the periodic schedule. if this bit is a zero then the status of the periodic schedule is disabled. if this bit is a one then the status of the periodic schedule is enabled. the host controller is not required to immediately disable or enable the periodic schedule when software transitions the periodic schedule enable bit in the usbcmd register. when this bit and the periodic schedule enable bit are the same value, the periodic schedule is either enabled (1) or disabled (0). 13 ro reclamation 0=default. this is a read-only status bit, which is used to detect an empty asynchronous schedule. the operational model of empty schedule detection is described in section 4.8.3 of the echi specification. the valid transitions for this bit are described in sect ion 4.8.6 of the echi specfication. 12 rw hchalted 1=default. this bit is a zero whenever the run/stop bit is a one. the host controller sets this bit to one after it has stopped executing as a result of the run/stop bit being set to 0, either by software or by the host controller hardware (e.g. internal error).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 154 m9999-031810-1.2 11:6 rw reserved. these bits are reserved and should be set to zero. 5 r/wc interrupt on async advance 0=default. system software can force the host cont roller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the interrupt on async advance doorbell bit in the usbcmd register. this status bit indicates the assertion of that interrupt source. 4 r/wc host system error the host controller sets this bit to 1 when a serious error occurs during a host system access involving the host controller module. in a pci syst em, conditions that set this bit to 1 include pci parity error, pci master abort, and pci target a bort. when this error occurs, the host controller clears the run/stop bit in the command register to prevent fu rther execution of the scheduled tds. 3 r/wc frame list rollover the host controller sets this bit to a one when the frame list index (s ee section 2.3.4 of the echi specification) rolls over from its maximu m value to zero. the exact value at which the rollover occurs depends on the frame list size. for ex ample, if the frame list size (as programmed in the frame list size field of the usbcmd regi ster) is 1024, the frame i ndex register rolls over every time frindex[13] toggles. sim ilarly, if the size is 512, the ho st controller sets this bit to a one every time frindex[12] toggles. 2 r/wc port change detect the host controller sets this bit to a one when any port for which the port owner bit is set to zero (see section 2.3.9) has a change bi t transition from a zero to a one or a force port resume bit transition from a zero to a one as a result of a j-k transition detected on a suspended port. this bit will also be set as a result of the connect status change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's port owner bit (see section 4.2.2 of the echi specification). this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that on a d3 to d0 transition of the ehci hc device, this bit is loaded with the or of all of the portsc change bits (including: force port re sume, over-current change, enable/disable change and connect status change). 1 r/wc usb error interrupt (usberrint) the host controller sets this bit to 1 when co mpletion of a usb transaction results in an error condition (e.g., error counter underflow). if the td on which the error interrupt occurred also had its ioc bit set, both this bit and usbint bit are se t. see section 4.15.1 for a list of the usb errors that will result in this bit being set to a one. 0 r/wc usb interrupt (usbint) the host controller sets this bit to 1 on the comp letion of a usb transaction, which results in the retirement of a transfer descr iptor that had its ioc bit set. the host controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the ex pected number of bytes).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 155 m9999-031810-1.2 2.18.5 echi operational register ? usbintr (usbopbase 0x08) bit field read/ write description 31:6 rw reserved. these bits are reserved and should be set to zero. 5 rw interrupt on async advance enable when this bit is a one, and the interrupt on async advance bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing the interrupt on async advance bit. 4 rw host system error enable when this bit is a one, and the host system error status bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the host system error bit. 3 rw frame list rollover enable when this bit is a one, and the frame list rollove r bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the frame list rollover bit. 2 rw port change interrupt enable when this bit is a one, and the port change detect bit in the usbsts register is a one, the host controller will issue an interrupt. the interrupt is acknowledged by software clearing the port change detect bit. 1 rw usb error interrupt enable when this bit is a one, and the usberrint bit in the usbsts register is a one, the host controller will issue an interrupt at the next interr upt threshold. the interrupt is acknowledged by software clearing the usberrint bit. 0 rw usb interrupt enable when this bit is a one, and the usbint bit in the usbsts register is a one, the host controller will issue an interrupt at the next interrupt thres hold. the interrupt is acknowledged by software clearing the usbint bit. note: for all enable register bits, 1= enabled, 0= disabled 2.18.6 echi operational register ? frindex (usbopbase 0x0c) bit field read/ write description 31:14 rw reserved. these bits are reserved and should be set to zero. 13:0 rw reserved. 13:0 frame index. the value in this register incr ements at the end of each time frame (e.g. micro- frame). bits [n:3] are used for the frame list cu rrent index. this means t hat each location of the frame list is accessed 8 times (frames or micr o-frames) before moving to the next index. the following illustrates values of n based on the value of the frame list size field in the usbcmd register. usbcmd[frame list size] number elements n 00b (1024) 12 01b (512) 11 10b (256) 10 11b reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 156 m9999-031810-1.2 the sof frame number value for the bus sof token is derived or alternatively managed from this register. please refer to section 4.5 of the echi specification for a detailed ex planation of the sof value management requirements on the host controller. the value of frindex must be 125 sec (1 micro-frame) ahead of the sof token value. the sof value may be implemented as an 11-bit shadow r egister. for this discussion, this shadow register is 11 bits and is named sofv. sofv updates every 8 micro-frames . (1 millisecond). an example implementation to achieve this behavior is to increment sofv each time the frindex[2:0] increments from a zero to a one. software must use the value of frindex to derive the current micro-frame number, both for high-speed isochronous scheduling purposes and to provide the get micro-frame number f unction required for client driv ers. therefore, the value of frindex and the value of sofv must be kept consistent if chip is reset or software writes to frindex. writes to frindex must also write-through frind ex[13:3] to sofv[10:0]. in order to keep the update as simple as possible, software should never write a frindex value where the thr ee least significant bits are 111b or 000b. please refer to section 4.5 of the e chi specification. 2.18.7 echi operational register ? ctrlssegment (usbopbase 0x10) bit field read/ write description 31:0 rw writes must be dword writes. this 32-bit register corresponds to the most significant address bits [63:32] for all ehci data structures. if the 64-bit addressing capability field in hccparams is a zero, then this r egister is not used. software cannot write to it and a read from this register will return zeros. if the 64-bit addressing capability field in hccparams is a one, then this register is used with the link pointers to construct 64-bit addresses to ehci control data structures. this register is concat enated with the link pointer from either the periodiclistbase, asynclistaddr, or any control data structure link fi eld to construct a 64-bit address. this register allows the host software to locate all control data structures with in the same 4 gigabyte memory segment. 2.18.8 echi operational register ? periodiclistbase (usbopbase 0x14) bit field read/ write description 31:12 rw base address (low). these bits correspond to memory addr ess signals [31:12], respectively. 11:00 rw reserved. must be written as 0s. during runtime, the values of thes e bits are undefined. this 32-bit register contains the beginni ng address of the periodic frame list in the system memory. if the host controller is in 64-bit mode (as indicated by a one in the 64-bit addressing capability field in the hccsparams register), then the most significant 32 bits of every cont rol data structure address comes from the ctrldssegment register (see section 2.3.5). system software loads this regist er prior to starting the schedule execution by the host controller (see 4.1). the memory structure referenced by this physical memory pointer is assumed to be 4-kbyte aligned. the contents of this register are combined with the frame index register (frindex) to enable t he host controller to step through the periodic frame list in sequence. 2.18.9 echi operational register ? asynclistaddr (usbopbase 0x18) bit field read/ write description 31:12 rw base address (low). these bits correspond to memory addr ess signals [31:12], respectively. 11:00 rw reserved. must be written as 0s. during runtime, the values of thes e bits are undefined.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 157 m9999-031810-1.2 this 32-bit register contains the address of the next asyn chronous queue head to be executed. if the host controller is in 64-bit mode (as indicated by a one in 64-bit addressing c apability field in the hccparams register), then the most significant 32 bits of every control dat a structure address comes from the ctrl dssegment register (see section 2.3.5 of echi specification). bits [4:0] of th is register cannot be modifi ed by system software and will always return a zero when read. the memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned. 2.18.10 ohci operational registers (0xd000 ? 0xdfff) the ohci operational registers are stored in this block of memory. register name offset from ohci ahb slave start address (0xd000) hcrevision usbopbase + 00h hccontrol usbopbase + 04h hccommandstatus usbopbase + 08h hcinterruptstatus usbopbase + 0ch hcinterruptenable usbopbase + 10h hcinterruptdisable usbopbase + 14h hchcca usbopbase + 18h hcperiodcurrented usbopbase + 1ch hccontrolheaded usbopbase + 20h hccontrolcurrented usbopbase + 24ch hcbulkheaded usbopbase +280h hcbulkcurrented usbopbase + 2ch hcdonehead usbopbase + 30h hcfminterval usbopbase + 34h hcfmremaining usbopbase + 38h hcfmnumber usbopbase + 3cch hcperiodicstart usbopbase + 40ch hclsthreshold usbopbase + 44h hcrhdescriptora usbopbase + 48h hcrhdescriptorb usbopbase + 4ch hcrhstatus usbopbase + 50h hcrhportstatus[1] usbopbase + 54h hcrhportstatus[ndp] usbopbase + 54+4h *ndp
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 158 m9999-031810-1.2 2.18.11 crevision register (0xd000) bit field read/ write description 31:8 rw reserved. 7:0 rw rev - revision default 10h hcd ? read hc ? read this read-only field contains the bcd representation of the version of the hci s pecification that is implemented by this hc. for example, a value of 11h corresponds to version 1.1. all of the hc implementations that are compliant with th is specification will have a value of 10h. 2.18.12 hccontrol register (0xd004) the hccontrol register defines the operating modes fo r the host controller. most of the fields in this register are modified only by the host controller driver, except h ostcontrollerfunctionalstate and remotewakeupconnected. bit field read/ write description 31:11 rw reserved. 10 rw rwe - remotewakeupenable this bit is used by hcd to enable or disable the remote wakeup feat ure upon the detection of upstream resume signaling. when this bi t is set and the resumedetected bit in hcinterruptstatus is set, a remote wakeup is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9 rw rwc - remotewakeupconnected this bit indicates whether hc supports remote wakeup signaling. if remote wakeup is supported and used by the system it is the responsibility of system firmware to set this bit during post. hc clears the bit upon a hardware reset but does not alter it upon a software reset. remote wakeup signaling of the host system is host-bus-specific and is not descr ibed in this specification. 8 rw ir - interruptrouting this bit determines the routing of in terrupts generated by events registered in hcinterruptstatus . i f clear, all interrupts are routed to the normal host bus interrupt mechanism. if set, interrupts are routed to the system management interrupt. hcd clears this bit upon a hardware reset, but it does not alter this bit upon a software reset. hcd uses this bit as a tag to indicate the ownership of hc 7:6 rw hcfs - hostcontrollerfunctionalstate for usb 00b: u sb r eset 01b: u sb r esume 10b: u sb o perational 11b: u sb s uspend a transition to u sb o perational from another state causes sof gener ation to begin 1 ms later. hcd may determine whether hc has begun sending sofs by reading the startofframe field of hcinterruptstatus . this field may be changed by hc only when in the u sb s uspend state. hc may move from the u sb s uspend state to the u sb r esume state after detecting the resume signaling from a downstream port. hc enters u sb s uspend after a software reset, whereas it enters u sb r eset after a hardware reset. the latter also resets the root hub and assert s subsequent reset signaling to downstream ports.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 159 m9999-031810-1.2 5 rw ble - bulklistenable this bit is set to enable the processing of the bulk list in the next frame. if cleared by hcd, processing of the bulk list does not occur after the next sof. hc checks this bit whenever it determines to process the list. when disabled, hcd may modify the list. if hcbulkcurrented is pointing to an ed to be removed, hcd must advance the pointer by updating hcbulkcurrented before re-enabling processing of the list. 4 rw cle - controllistenable this bit is set to enable the processing of the control list in the next frame. if cleared by hcd, processing of the control list does not occur afte r the next sof. hc must check this bit wheneve r it determines to process the list. w hen disabled, hcd may modify the list. if hccontrolcurrented is pointing to an ed to be removed, hcd must advance the pointer by updating hccontrolcurrented before re-enabling processing of the list. 3 rw ie - isochronousenable this bit is used by hcd to enable/disable proce ssing of isochronous eds. while processing the periodic list in a frame, hc checks the status of this bit when it finds an isochronous ed (f=1). i f set (enabled), hc continues processing the eds. if cleared (disabled), hc halts processing of the periodic list (which now contains only isochr onous eds) and begins processing the bulk/control lists. setting this bit is guaranteed to take effe ct in the next frame ( not the current frame). 2 rw ple - periodiclistenable this bit is set to enable the processing of the periodic list in the next frame. if cleared by hcd, processing of the periodic list does not occur after the next sof. hc must check this bit before it starts processing the list. 1:0 rw cbsr - controlbulkserviceratio this specifies the service rati o between control and bulk eds. before processing any of the nonperiodic lists, hc must compare the ratio spec ified with its internal count on how man y nonempty control eds have been proc essed, in determining whether to continue serving anothe r control ed or switching to bulk eds. the in ternal count will be retained when crossing the frame boundary. in case of reset, hcd is res ponsible for restoring this value. cbsr no. of control eds over bulk eds served 0 1:1 1 2:1 2 3:1 3 4:1 2.18.13 hccommandstatus register (0xd008) bit field read/ write description 31:18 rw reserved. 17:16 rw soc - schedulingoverruncount these bits are incremented on each scheduling ove rrun error. it is initialized to 00b and wraps around at 11b. this will be incremented when a scheduling overrun is detected even if schedulingoverrun in hcinterruptstatus has already been set. this is used by hcd to monitor any persistent scheduling problems. 15:4 rw reserved 3 rw ocr - ownershipchangerequest this bit is set by an os hcd to request a change of control of the hc. when set hc will set the ownershipchange field in hcinterruptstatus . after the changeover, this bit is cleared and remains so until the next request from os hcd.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 160 m9999-031810-1.2 2 rw blf - bulklistfilled this bit is used to indicate whether there are any tds on the bulk list. it is set by hcd whenever it adds a td to an ed in the bulk list. when hc begins to process the head of the bulk list, it checks bf. as long as bulklistfilled is 0, hc will not start processing the bulk list. if bulklist filled is 1, hc will start processing the bulk list and will set bf to 0. if hc finds a td on the lis t, then hc will set bulklistfilled to 1 causing the bulk list processing to continue. if no td is found on the bulk list, and if hcd does not set bulklistfilled, then bulklistf illed will still be 0 when hc completes processing the bulk list and bulk list processing will stop. 1 rw clf - controllistfilled this bit is used to indicate whether there ar e any tds on the control list. it is set by hcd whenever it adds a td to an ed in the control list. when hc begins to process the head of the c ontrol list, it checks clf. as long as controllistfilled is 0, hc will not start processing the control list. if cf is 1, hc will start processing the control list and will set controllistf illed to 0. if hc finds a td on the list, then hc will set controllistfilled to 1 causing the control list processing to continue. if no td is found on the control list, and if the hcd does not set controllistfilled, t hen controllistfilled will still be 0 when hc completes processing the control list and control list processing will stop. 0 rw hcr - hostcontrollerreset this bit is set by hcd to initiate a software reset of hc. regardless of t he functional state of hc, it moves to the u sb s uspend state in which most of the operati onal registers are reset except those stated otherwise; e.g., the interruptrouting field of hccontrol, and no host bus accesses are allowed. this bit is cleared by hc upon the comple tion of the reset operation. the reset operation must be completed within 10 s. this bit, when set, should not cause a reset to the root hub and no subsequent reset signaling should be asserted to its downstream ports. 2.18.14 hcinterruptstatus register (0xd00c) this register provides status on vari ous events that cause hardware interrupts. when an event occurs, host controller sets the corresponding bit in this register. when a bit becom es set, a hardware interrupt is generated if the interrupt is enabled in the hcinterruptenable register (see section 7.1.5 of the ochi specification) and the masterinterruptenable bit is set. the host controller driver may clear specific bits in this register by writing ?1? to bit positions to be cleared. the host controller driver may not set any of these bits. the host controller will never clear the bit. bit field read/ write description 31 rw mie ? hcd ? rw hc ? r a ?0? written to this field is ignored by hc. a '1' written to this field enables interrupt generation due to events specified in the other bits of this register. this is used by hcd as a master interrupt enable. 30 rw oc ? ownershipchange hcd ? rw hc - rd 0 - ignore 1 - enable interrupt generation due to ownership change. 29:07 rw reserved 6 rw rhsc ? roothubstatuschange hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to root hub status change.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 161 m9999-031810-1.2 5 rw fno ? framenumberoverflow hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to frame number overflow. 4 rw ue ? unrecoverableerror hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to unrecoverable error. 3 rw rd ? resumedetected hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to resume detect. 2 rw sf ? startofframe hcd ? rw hc - r 0 - ignore 1 - enable interrupt generati on due to start of frame. 1 rw wdh ? writebackdonehead hcd ? rw hc - r 0 - ignore 1 - enable interrupt generati on due to hcdonehead writeback. 0 rw so ? schedulingoverrun hcd ? rw hc - r 0 - ignore 1 - enable interrupt generati on due to scheduling overrun. 2.18.15 hcinterrupt enable register (0xd010) each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events gener ate a hardware interrupt. when a bit is set in the hcinterruptstatus register and the corresponding bit in the hcinterruptenable register is set and the masterinterruptenable bit is set, then a hardware inte rrupt is requested on the host bus. writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit unchanged. on read, the current value of this register is returned. bit field read/ write description 31 rw mie ? default = 0b hcd ? rw hc ? r a ?0? written to this field is ignored by hc. a '1' written to this field enables interrupt generation due to events specified in the other bits of this register. this is used by hcd as a master interrupt enable.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 162 m9999-031810-1.2 30 rw oc ? ownershipchange default = 0b hcd ? rw hc - rd 0 - ignore 1 - enable interrupt generation due to ownership change. 29:07 rw reserved 6 rw rhsc ? roothubstatuschange default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to root hub status change. 5 rw fno ? framenumberoverflow default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to frame number overflow. 4 rw ue ? unrecoverableerror default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to unrecoverable error. 3 rw rd ? resumedetected default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generation due to resume detect. 2 rw sf ? startofframe default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generati on due to start of frame. 1 rw wdh ? writebackdonehead default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generati on due to hcdonehead writeback.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 163 m9999-031810-1.2 0 rw so ? schedulingoverrun default = 0b hcd ? rw hc - r 0 - ignore 1 - enable interrupt generati on due to scheduling overrun. 2.18.16 hcinterrupt disable register (0xd014) each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. thus, writing a '1' to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on read, the current value of the hcinterruptenable register is returned. bit field read/ write description 31 rw mie ? default = 0b hcd ? rw hc ? r a ?0? written to this field is ignored by hc. a '1 ' written to this field disables interrupt generation due to events specified in the other bits of this register. this field is set after a hardware o r software reset. 30 rw oc ? ownershipchange default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generation due to ownership change. 29:07 rw reserved 6 rw rhsc ? roothubstatuschange default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generation due to root hub status change. 5 rw fno ? framenumberoverflow default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generation due to frame number overflow. 4 rw ue ? unrecoverableerror default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generation due to unrecoverable error.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 164 m9999-031810-1.2 3 rw rd ? resumedetected default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generation due to resume detect. 2 rw sf ? startofframe default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generati on due to start of frame. 1 rw wdh ? writebackdonehead default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generati on due to hcdonehead writeback. 0 rw so ? schedulingoverrun default = 0b hcd ? rw hc - r 0 - ignore 1 - disable interrupt generati on due to scheduling overrun. 2.18.17 hchcca register (0xd018) the hchcca register contains the physical addr ess of the host controller communi cation area. the host controller driver determines the alignment rest rictions by writing all 1s to hchcca and reading the content of hchcca . the alignment is evaluated by examining the num ber of zeroes in the lower order bits. the minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. detailed description can be found in chapter 4 of the ohci specification. this area is used to hol d the control structures and the interrupt table that are access ed by both the host controller and the host controller driver. bit field read/ write description 31:8 rw hcca host controller communications area. default 0h hcd ? rw hc ? r this is the base address of the ho st controller communication area. 7:0 - default 0h
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 165 m9999-031810-1.2 2.18.18 hcperiodcurrented register (0xd01c) the hcperiodcurrented register contains the physical address of the current isochronous or interrupt endpoint descriptor. bit field read/ write description 31:4 rw pced periodcurrented default 0h hcd ? r hc ? rw this is used by hc to point to the head of one of the periodic lists which will be processed in the current frame. the content of this register is updated by hc after a periodic ed has been processed. hcd may read the c ontent in determining which ed is currently being processed at the time of reading. 3:0 - default 0h 2.18.19 hccontrolheaded register (0xd020) the hccontrolheaded register contains the physical address of t he first endpoint descriptor of the control list. bit field read/ write description 31:4 rw ched controlheaded default 0h hcd ? rw hc ? r hc traverses the control list starting with the hccontrolheaded pointer. the content is loaded from hcca during the in itialization of hc. 3:0 - default 0h 2.18.20 hccontrolcurrented register (0xd024) the hccontrolcurrented register contains the physical address of the current endpoint descriptor of the control list. bit field read/ write description 31:4 rw cced controlcurrented default 0h hcd ? rw hc ? rw this pointer is advanced to the next ed after se rving the present one. hc will continue processing the list from where it left off in the last fram e. when it reaches the end of the control list, hc checks the controllistfilled of in hccommandstatus . if set, it copies the content o f hccontrolheaded to hccontrolcurrented and clears the bit. if not set, it does nothing. hcd is allowed to modify this register only when the controllistenable of hccontrol is cleared. when set, hcd only reads the instantaneous va lue of this register. initially, this is set to zero to indicate the end of the control list. 3:0 - default 0h
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 166 m9999-031810-1.2 2.18.21 hcbulkheaded register (0xd028) the hcbulkheaded register contains the physical address of t he first endpoint descriptor of the bulk list. bit field read/ write description 31:4 rw bhed bulkheaded default 0h hcd ? rw hc ? r hc traverses the bulk list starting with the hcbulkheaded pointer. the content is loaded from hcca during the init ialization of hc. 3:0 - default 0h 2.18.22 hcbulkcurrented register (0xd02c) the hcbulkcurrented register contains the physical addr ess of the current endpoint of the bulk list. as the bulk list will be served in a round-robin fashion, the endpoints will be ordered according to their insertion to the list. bit field read/ write description 31:4 rw bced bulkcurrented default 0h hcd ? rw hc ? rw this is advanced to the next ed after the hc has served the present one. hc continues processing the list from where it left off in the last frame. when it reaches the end of the bulk list, hc checks the controllistfilled of hccontrol. if set, it copies the content of hcbulkheaded to hcbulkcurrented and clears the bit. if it is not set, it does nothing. hcd is only allowed to modify this register when t he bulklistenable of hccontrol is cleared. when set, the hcd only reads the instantaneous value of this register. this is initially set to zero to indicate the end of the bulk list. 3:0 - default 0h 2.18.23 hcdonehead register (0xd030) the hcdonehead register contains the physical address of the last completed transfe r descriptor that was added to the done queue. in normal operation, the host controller driver should not need to read this register as its content is periodically written to the hcca. bit field read/ write description 31:4 rw dh donehead default 0h hcd ? r hc ? rw when a td is completed, hc writes the content of hcdonehead to the nexttd field of the td. hc then overwrites the content of hcdonehead with the address of this td. this is set to zero whenever hc writes the content of this register to hcca. it also sets the writebackdonehead of hcinterruptstatus . 3:0 - default 0h
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 167 m9999-031810-1.2 2.18.24 hcfminterval register (0xd034) the hcfminterval register contains a 14-bit value which indicates t he bit time interval in a frame, (i.e., between two consecutive sofs), and a 15-bit value indicating the full speed maximum packet size that the host controller may transmit or receive without causing scheduling overrun. the host controller dr iver may carry out minor adjustment on the frameinterval by writing a new value over the present one at each sof. this provides the programmability necessary for the host controller to sy nchronize with an external clocking res ource and to adjust any unknown local clock offset. bit field read/ write description 31 rw fit frameintervaltoggle default = 0h hcd ? rw hc ? r hcd toggles this bit whenever it loads a new value to frameinterval. 30:16 rw fsmps fslargestdatapacket default = tbd this field specifies a value which is loaded into the largest data packet counter at the beginning of each frame. the counter val ue represents the largest amount of data in bits which can be sent or received by the hc in a single transaction at any given time without causing scheduling overrun. the field value is calculated by the hcd. 15:14 rw reserved 13;0 rw fi frameinterval default = 2edfh this specifies the interval between two consecutive sofs in bit times. the nominal value is set to be 11,999. hcd should store the current value of this field before resetting hc. by setting the hostcontrollerreset field of hccommandstatus as this will cause the hc to reset this field to its nominal value. hcd may choose to restore t he stored value upon the completion of the reset sequence. 2.18.25 hcfmremaining register (0xd038) the hcfmremaining register is a 14-bit down counter showing the bit time remaining in the current frame. bit field read/ write description 31 rw frt frameremainingtoggle default = 0h hcd = r hc = r this bit is loaded from the frameintervaltoggle field of hcfminterval whenever frameremaining reaches 0. this bit is used by hcd for the synchronization bet ween frameinterval and frameremaining. 30:14 - reserved 13:0 frameremaining this counter is decremented at each bit time. w hen it reaches zero, it is reset by loading the frameinterval value specified in hcfminterval at the next bit time boundary. when entering the u sb o perational state, hc re-loads the content with the frameinterval of hcfminterval and uses the updated value from the next sof.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 168 m9999-031810-1.2 2.18.26 hcfmnumber register (0xd03c) the hcfmnumber register is a 16-bit counter. it provides a timing reference among events happening in the host controller and the host controller driver. the host controller driver may use the 16- bit value specified in this register and generate a 32-bit frame number without r equiring frequent access to the register. bit field read/ write description 31:16 rw reserved 15:0 rw fn framenumber default = 0h hcd = r hc = rw this is incremented when hcfmremaining is re-loaded. it will be rolled over to 0h after ffffh. when entering the u sb o perational state, this will be incremented automatically. the content will be written to hcca after hc has incremented the framenumber at each frame boundary and sent a sof but before hc reads the first ed in that frame. after writing to hcca, hc will set the startofframe in hcinterruptstatus. 2.18.27 hcperiodicstart register (0xd040) the hcperiodicstart register has a 14-bit programmable value which determines when is the earliest time hc should start processing the periodic list. bit field read/ write description 31:14 rw reserved 13:0 rw ps periodicstart default = 0h hcd = rw hc = r after a hardware reset, this field is cleared. this is then set by hcd during the hc initialization. the value is calculated roughly as 10% off from hcfminterval . a typical value will be 3e67h. when hcfmremaining reaches the value specified, processing of the periodic lists will have priority over control/bulk processing. hc will therefore start processing the interrupt list after completing the current control or bulk transaction that is in progress. 2.18.28 hclsthreshold register (0xd044) the hclsthreshold register contains an 11-bit value used by the host controller to determine whether to commit to the transfer of a maximum of 8-byte ls packet before eof. neit her the host controller nor t he host controller driver are allowed to change this value. bit field read/ write description 31:12 rw reserved 11:0 rw lst lsthreshold default = 0628h hcd = rw hc = r this field contains a value which is compared to the frameremaining field prior to initiating a low speed transaction. the transaction is started only if frameremaining this field. the value is calculated by hcd with the considerat ion of transmission and setup overhead.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 169 m9999-031810-1.2 2.18.29 hcrhdescriptora register (0xd048) the hcrhdescriptora register is the first register of two describing t he characteristics of the root hub. reset values are implementation-specific. the descriptor length (11), descriptor type (tbd), and hub controller current (0) fields of the hub class descriptor are emulated by the hcd. all other fields are located in the hcrhdescriptora and hcrhdescriptorb registers. bit field read/ write description 31:24 rw potpgt powerontopowergoodtime default = is hcd ? rw hc ? r this byte specifies the duration hcd has to wa it before accessing a power ed-on port of the root hub. it is implementation-specific. the unit of time is 2 ms. the duration is calculated as potpgt * 2 ms. 23:13 rw reserved 12 rw nocp noovercurrentprotection default = is hcd ? rw hc - r this bit describes how the overcurrent status for t he root hub ports are reported. when this bit is cleared, the overcurrentprot ectionmode field specifies gl obal or per-port reporting. 0: over-current status is reported collectively for all downstream ports 1: no overcurrent protection supported 11 rw ocpm overcurrentprotectionmode default = is hcd ? rw hc - r this bit describes how the overcurrent status for the root hub ports are reported. at reset, this fields should reflect the same mode as powerswi tchingmode. this field is valid only if the noovercurrentprotection field is cleared. 0: over-current status is reported collectively for all downstream ports 1: over-current status is reported on a per-port basis 10 rw dt devicetype default = 0b hcd ? r hc - r this bit specifies that the root hub is not a compound device. the root hub is not permitted to be a compound device. this field should always read/write 0.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 170 m9999-031810-1.2 9 rw nps nopowerswitching default = is hcd ? rw hc - r these bits are used to specify whether power swit ching is supported or port are always powered. it is implementation- specific. when this bit is cleared, the powerswi tchingmode specifies global or per-port switching. 0: ports are power switched 1: ports are always powered on when the hc is powered on 8 rw psm powerswitchingmode default = is hcd ? rw hc - r this bit is used to specify how the power switchi ng of the root hub ports is controlled. it is implementation-specific. this field is only va lid if the nopowerswitching field is cleared. 0: all ports are powered at the same time. 1: each port is powered individually. this mode a llows port power to be controlled by either the global switch or per-port switching. if the port powercontrolmask bit is set, the port responds only to port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). 7:0 rw ndp numberdownstreamports default = is hcd ? r hc - r these bits specify the number of downstream ports supported by the root hub. it is implementation-specific. the mi nimum number of ports is 1. the maximum number of ports supported by openhci is 15.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 171 m9999-031810-1.2 2.18.30 hcrhdescriptorb register (0xd04c) the hcrhdescriptorb register is the second register of two describing the characteristics of the root hub. these fields are written during initialization to corres pond with the system implementation. re set values are implementation-specific. bit field read/ write description 31:16 rw ppcm portpowercontrolmask default ? is hcd = rw hc = r each bit indicates if a port is affected by a global power control command when powerswitchingmode is set. when set, the port's pow er state is only affected by per-port power control (set/clearportpower). when cleared, the port is controll ed by the global power switch (set/clearglobalpower). if the device is configured to global switching mode (powerswitchingmode=0), this field is not valid. bit 0: reserved bit 1: ganged-power mask on port #1 bit 2: ganged-power mask on port #2 ... bit15: ganged-power mask on port #15 15:0 rw dr deviceremovable default = is hcd = rw hc = r each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 0: reserved bit 1: device attached to port #1 bit 2: device attached to port #2 ... bit15: device attached to port #15 2.18.31 hcrhstatus register (0xd050) the hcrhstatus register is divided into two parts. t he lower word of a dword represents the hub status field and the upper word represents the hub status change field. reserved bits should always be written '0'. bit field read/ write description 31 rw crwe clearremotewakeupenable (write only) hcd = w hc = r writing a '1' clears deviceremovewakeupenable. writing a '0' has no effect. 30:18 - reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 172 m9999-031810-1.2 17 rw ocic overcurrentindicatorchange default = 0b hcd = rw hc = r each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 0: reserved bit 1: device attached to port #1 bit 2: device attached to port #2 ... bit15: device attached to port #15 16 rw lpsc (read) localpowerstatuschange default = 0b hcd = rw hc = r the root hub does not support the loca l power status feature; thus, th is bit is always read as ?0?. (write) setglobalpower in global power mode (powerswitchingmode=0), this bi t is written to ?1? to turn on power to all ports (clear portpowerstatus). in per-port pow er mode, it sets portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing a ?0? has no effect. 15 rw drwe (read) deviceremotewakeupenable default = 0b hcd = r hc = rw this bit enables a connectstatuschange bit as a resume event, causing a usbsuspend to usbresume state transition and setting the resumedetected interrupt. 0 = connectstatuschange is not a remote wakeup event. 1 = connectstatuschange is a remote wakeup event. (write) setremotewakeupenable writing a '1' sets deviceremovewakeupenable. writing a '0' has no effect. 14:2 - reserved 1 rw oci overcurrentindicator default = 0b hcd = r hc = rw this bit reports overcurrent conditions when t he global reporting is implemented. when set, an overcurrent condition exists. when cleared, a ll power operations are normal. if per-port overcurrent protection is implem ented this bit is always ?0?
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 173 m9999-031810-1.2 0 rw lps (read) localpowerstatus default = 0b hcd = rw hc = r the root hub does not support the loca l power status feature; thus, th is bit is always read as ?0?. (write) clearglobalpower in global power mode (powerswitchingmode=0), this bi t is written to ?1? to turn off power to all ports (clear portpowerstatus). in per-port pow er mode, it clears portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing a ?0? has no effect. 2.18.32 hcrhportstatus[1:ndp] register (0xd054) the hcrhportstatus [1:ndp] register is used to control and report port events on a per-port basis. numberdownstreamports r epresents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to reflect the port stat us, whereas the upper word reflects the st atus change bits. some status bits are implemented with special write behavior (see below). if a transaction (token through handshak e) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. reserved bits should always be written '0'. bit field read/ write description 31:21 rw reserved 20 rw prsc portresetstatuschange default = 0b hcd = rw hc = rw this bit is set at the end of the 10-ms port reset signal. the hcd writes a ?1? to clear this bit. writing a ?0? has no effect. 0 = port reset is not complete 1 = port reset is complete 19 rw ocic portovercurrentindicatorchange default = 0b hcd = rw hc = rw this bit is valid only if overcurrent conditions ar e reported on a per-port basis. this bit is set when root hub changes the portovercurrentindicator bit. the hcd writes a ?1? to clear this bit. writing a ?0? has no effect. 0 = no change in portovercurrentindicator 1 = portovercurrentindicator has changed
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 174 m9999-031810-1.2 18 rw pssc portsuspendstatuschange default = 0b hcd = rw hc = rw this bit is set when the full resume sequence has been completed. this sequence includes the 20-s resume pulse, ls eop, and 3-ms resychroniza tion delay. the hcd writes a ?1? to clear this bit. writing a ?0? has no effect. this bi t is also cleared when resetstatuschange is set. 0 = resume is not completed 1 = resume completed 17 rw pesc portenablestatuschange default = 0b hcd = rw hc = rw this bit is set when hardware events cause the po rtenablestatus bit to be cleared. changes from hcd writes do not set this bit. the hcd writes a ?1? to clear this bit. writing a ?0? has no effect. 0 = no change in portenablestatus 1 = change in portenablestatus 16 rw csc connectstatuschange default =0b hcd = rw hc = rw this bit is set whenever a connect or disconnect event occurs. the hcd writes a ?1? to clear this bit. writing a ?0? has no effect. if current connectstatus is cleared when a setportreset, setportenable, or setportsuspend write occurs, this bi t is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0 = no change in currentconnectstatus 1 = change in currentconnectstatus note: if the deviceremovable[ndp] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15:10 - reserved 9 rw lsda (read) lowspeeddeviceattached default =xb hcd = rw hc = rw this bit indicates the speed of the device attac hed to this port. when set, a low speed device is attached to this port. when clear, a full speed device is attached to this port. this field is valid only when the currentconnectstatus is set. 0 = full speed device attached 1 = low speed device attached (write) clearportpower the hcd clears the portpowerstatus bit by writing a ?1? to this bit. writing a ?0? has no effect.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 175 m9999-031810-1.2 8 rw pps (read) portpowerstatus default = 0b hcd = rw hc = rw this bit reflects the port?s power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. hcd sets this bit by writing setportpower or setglobalpower. hcd clears this bit by writing clearportpower or clearglobalpower. which power contro l switches are enabled is determined by powerswitchingmode and portportcontrolm ask[ndp]. in global switching mode (powerswitchingmode=0), only set/clearglobalpowe r controls this bit. in per-port power switching (powerswitchingmode=1), if the portpowercontrolmask[ndp] bit for the port is set, only set/clearportpower commands are enabled. if t he mask is not set, only set/clearglobalpower commands are enabled. when port power is disabl ed, currentconnectstatus, portenablestatus, portsuspendstatus, and portre setstatus should be reset. 0 = port power is off 1 = port power is on (write) setportpower the hcd writes a ?1? to set the portpowers tatus bit. writing a ?0? has no effect. note: this bit is always reads ?1b? if power switching is not supported. 7:5 - reserved 4 rw prs (read) portresetstatus default = 0b hcd = rw hc = rw when this bit is set by a write to setportrese t, port reset signaling is asserted. when reset is completed, this bit is cleared when portresets tatuschange is set. this bit cannot be set if currentconnectstatus is cleared. 0 = port reset signal is not active 1 = port reset signal is active (write) setportreset the hcd sets the port reset signaling by writing a ?1 ? to this bit. writing a ?0? has no effect. if currentconnectstatus is cleared, this write does not set portresetstatus, but instead sets connectstatuschange. this informs the driver t hat it attempted to reset a disconnected port. 3 rw poci (read) portovercurrentindicator default = 0b hcd = rw hc = rw this bit is only valid when the root hub is configured in such a way that overcurrent conditions are reported on a per-port basis. if per-port overcurrent r eporting is not supported, this bit is set to 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always reflects the overcurrent input signal 0 = no overcurrent condition. 1 = overcurrent condition detected. (write) clearsuspendstatus the hcd writes a ?1? to initiate a resume. writing a ?0? has no effect. a resume is initiated only if portsuspendstatus is set.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 176 m9999-031810-1.2 2 rw pss (read) portsuspendstatus default = 0b hcd = rw hc = rw this bit indicates the port is suspended or in the resume sequence. it is set by a setsuspendstate write and cleared when portsu spendstatuschange is set at the end of the resume interval. this bit cannot be set if current connectstatus is cleared. this bit is also cleared when portresetstatuschange is set at the end of t he port reset or when the hc is placed in the usbresume state. if an upstream resume is in progress, it shoul d propagate to the hc. 0 = port is not suspended 1 = port is suspended (write) setportsuspend the hcd sets the portsuspendstatus bit by writing a ?1 ? to this bit. writing a ?0? has no effect. if currentconnectstatus is cleared, this write does not set portsuspendstatus; instead it sets connectstatuschange. this informs the driver t hat it attempted to suspend a disconnected port. 1 rw pes (read) portenablestatus default = 0b hcd = rw hc = rw this bit indicates whether the port is enabled or di sabled. the root hub may clear this bit when an overcurrent condition, disconnect event, switched- off power, or operational bus error such as babble is detected. this change also causes portenabledstatuschange to be set. hcd sets this bit by writing setportenable and clears it by writ ing clearportenable. this bit cannot be set when currentconnectstatus is cleared. this bit is also set, if not already, at the completion of a port reset when resetstatuschange is set or port suspend when suspendstatuschange is set. 0 = port is disabled 1 = port is enabled (write) setportenable the hcd sets portenablestatus by writing a ?1?. writing a ?0? has no effect. if currentconnectstatus is cleared, this write does not set portenablestatus, but instead sets connectstatuschange. this informs the driver that it attempted to enable a disconnected port. 0 rw ccs (read) curentconnectstatus default = 0b hcd = rw hc = rw this bit reflects the current state of the downstream port. 0 = no device connected 1 = device connected (write) clearportenable the hcd writes a ?1? to this bit to clear the portenablestatus bit. writing a ?0? has no effect. the currentconnectstatus is not affected by any write. note: this bit is always read ?1b? when the attached device is nonremovable (deviceremoveable[ndp]).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 177 m9999-031810-1.2 2.19 uart registers (0xe000-0xe1ff) 2.19.1 uart 1 receive buffer register (ur1rb offset 0xe000) 2.19.2 uart 2 receive buffer register (ur2rb offset 0xe080) 2.19.3 uart 3 receive buffer register (ur3rb offset 0xe100) 2.19.4 uart 4 receive buffer register (ur4rb offset 0xe180) the uart receive buffer register contains an 8-bit data value received over the uart channel. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:0 -- ro urrbd uart receive buffer data this field contains the data received over the single channel uart. when uart finishes receiving data frame, the rece ive data ready bit in the line status register will be set. note: whenever the urrbd is read, the receive data ready bit in the line status register is automatically cleared. 2.19.5 uart 1 transmit holding register (ur1th offset 0xe004) 2.19.6 uart 2 transmit holding register (ur2th offset 0xe084) 2.19.7 uart 3 transmit holding register (ur3th offset 0xe104) 2.19.8 uart 4 transmit holding register (ur4th offset 0xe184) the uart transmit holding register contains an 8-bi t data value to be transmitted over the uart channel. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:0 -- wo urthd uart transmit holding data this field contains the data to be tr ansmitted over the single channel uart. whenever the urthd is written, the transmi t holding register empty bit in the line status register is automatically cleared to ?0? until the uart finishes transmitting the data. note: software should ensure that the trans mit holding register empty bit in the line status register is ?1? before writing to this regist er to prevent from over- writting the current transmit data. 2.19.9 uart 1 fifo control register (ur1fc offset 0xe008) 2.19.10 art 2 fifo control register (ur2fc offset 0xe088) 2.19.11 uart 3 fifo control register (ur3fc offset 0xe108) 2.19.12 uart 4 fifo control register (ur4fc offset 0xe188)
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 178 m9999-031810-1.2 the uart fifo control register provides control over transmitter and receiver fifos. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:6 00 rw urfrt uart receive fifo trigger level this field controls the trigger level for the receive fifo. 00 = 1 byte 01 = 8 bytes 10 = 16 bytes 11 = 24 bytes 5:3 000 ro reserved 2 0 rw urtfr uart transmit fifo reset when set, the transmit state machine will be reset, and the transmit fifo will be emptied. writing ?0? has no effect. note: this bit will be self-cleared to 0 after 1 is written. 1 0 rw urrfr uart receive fifo reset when set, the receive fifo state machi ne will be reset, and receive fifo will be emptied. writting ?0? has no effect. note: this bit will be self-cleared to 0 after 1 is written. 0 0 rw urfe uart fifo enable when set, both the transmit and receive fifos are enabled. (uart is in 16550 mode) when reset, both the transmit and receive fifos are disabled. (uart is in 16450 mode) note that when uart changes from fifo to character mode or vice versa, data in the fifos are automatically cleared. this bit must be set when other control bits in this register are written to or they will not be programmed. 2.19.13 uart 1 line control register (ur1lc offset 0xe00c) 2.19.14 uart 2 line control register (ur2lc offset 0xe08c) 2.19.15 uart 3 line control register (ur3lc offset 0xe10c) 2.19.16 uart 4 line control register (ur4lc offset 0xe18c)
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 179 m9999-031810-1.2 the uart line control register basica lly specifies the asynchronous data fram e for transmitting and receiving as seen below. start character length (5, 6, 7 or 8 bits) parity stop bits idle idle data transmitting direction fsample frclk 7,8,9 when the bus (one bit serial bus) is idle, it stays at high. the first high-to-low tr ansition is detected as the start bit. sta rt bit is low and stop bit is high. due to the noise, a shor t glitch might happen on the bus. to avoid detecting the wrong start bit, three samples at clock (frclk) 7, 8, and 9 after high- to-low transition is taken on t he bus. if at least two out of three samples are low, then start bit is detected; otherwise, the high-to-low transition is treated as a glitch. frclk and fsample will be defined at baud rate divisor register section. the following table shows the register bit fields. bit field default value read/ write description 31:10 0x0 ro reserved 9 0 rw cts_n tx flow control enable whet set, the data transmission is halt ed when the corresponding cts_n pin is high. when reset, no tx flow control is applied. [note: the cts_n and rts_n are shared with gpio pins. the bit23:21 in gpio port control register has to be configur ed to indicate which application is used.] 8 0 rw rts_n rx flow control enable when set, the corresponding rts_n pin will be desserted when the rx buffer level is greater than or equal to hwm trigger level. sending out a desserted value of rts_n will make the link partner stop to s end out data. when the rx buffer level is less than lwm trigger level, the corre sponding rts_n pin will be asserted. when reset, no rx flow control is applied. the following table shows the hwm and lwm tr igger level at different fifo size mode. fifo size hwm trigger level lwm trigger level 1 8 1 8 16 4 16 24 8 24 28 16 7 0 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 180 m9999-031810-1.2 6 0 rw ursbc uart set break condition on utxd when set, a break condition will be assert ed on the utxd pin. a break condition is when the utxd is driven low for mo re than one frame time ( including start, parity, and stop bits) measured at a give baud rate. 5 0 rw urspb uart stick parity bit when set, the stick parity is enabled, ( stick parity has pr ecedence over even/odd parity), i.e. if bit urpe, urepb, and urspb ar e all 1?s, parity is always 0. if bits urpe, and urspb are 1?s, and bit urepb is 0, parity is always 1. when reset, stick parity is disabled. 4 0 rw urepb uart even parity bit 0 = even parity. 0 = odd parity. 3 0 rw urpe uart parity enable (even/odd/stick) when set, parity is enabled. when reset, parity is disabled. 2 0 rw ursb uart stop bits 0 = 1 stop bit per data frame. 1 = 2 stop bit per data frame. 1:0 11 rw urcl uart character length 00 = 5 data bits per frame. 01 = 6 data bits per frame. 10 = 7 data bits per frame. 11 = 8 data bits per frame. (default) 2.19.17 uart 1 modem control register (ur1mc offset 0xe010) 2.19.18 uart 2 modem control register (ur2mc offset 0xe090) 2.19.19 uart 3 modem control register (ur3mc offset 0xe110) 2.19.20 uart 4 modem control register (ur4mc offset 0xe190) the uart 1 modem control register pr ovides interface with the modem. a ll the uart and modem communication uses software handshaing. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7 0 rw uren uart enable 1 = enable this uart unit, clock and io 0 = diable this uart unit, clock, and io 6:5 0 rw urclksel uart clock select 00 = 25mhz 01 = 62.5 mhz 10 = 125 mhz 11 = 166 mhz
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 181 m9999-031810-1.2 4 0 rw urlb uart loop back mode when set, the uart is in the local loopba ck mode. this feature is for software diagnostics/testing. when reset, the uart is in normal functional mode. note: in the uart loopback mode, the in terrupt mechanism is fully operational. the operation of the modem in the loopback mode is similar to external modem loopback with null modem cable. 3 0 rw urout2 uart out2 when set, the internal uart out2 signal is asserted to 0. when reset, the internal uart out2 signal is deasserted. 2 0 rw urout1 uart out1 when set, the internal uart out1 signal is asserted to 0. when reset, the internal uart out1 signal is deasserted. 1 0 rw reserved. 0 0 rw reserved 2.19.21 uart 1 line status register (ur1ls offset 0xe014) 2.19.22 uart 2 line status register (ur2ls offset 0xe094) 2.19.23 uart 3 line status register (ur3ls offset 0xe114) 2.19.24 uart 4 line status register (ur4ls offset 0xe194) the uart line status register provides status information to the cpu regarding the received data. the receive fifo has 16 entries, each of which includes one byte of data and three e rror bits (parity error, framing error,and break interrupt) associated to the data. the line status register is read only; writing to this register has no effect. the following table shows the register bit fields. bit field default value read/ write description 31:14 0x0 ro reserved 13:8 0x0 ro nadrf number of av ailable data in receive fifo 7 0 ro urrfe uart receive fifo error this bit is meaningful only in fifo mode to indicate that the uart receive fifo contains error(s). reading of ?1? indicates there is at leas t one of the following errors: parity error, framing error, or break interrupt. this bit is cleared only when it is r ead by cpu and no subsequent errors in the fifo. 6 1 ro urte uart transmit empty this bit indicates that the uart tranmit buffer is ready to accept new data for transmit. in character mode (16450): when set to ?1?, it indicates that t he transmit holding register and transmitter shift register are both empty. in fifo mode (16550): when set to ?1?, it indicates that both the transmit fifo and transmit shift register are empty
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 182 m9999-031810-1.2 5 1 ro urthre uart transmit holding register empty this bit indicates that the uart trans mit holding register (thr) is empty. in character mode (16450): when set to ?1?, it indicates the thr is empty. in fifo mode (16550): when set to ?1?, it indicates that the transmit fifo is empty. 4 0 ro urbi uart break interrupt indicator in character mode (16450): when set, it indicates a ?break? condition occurs on the urxd pin. a break condition is when the serial data is dr iven low for more than one frame time ( including start, parity, and stop bits) measured at a give baud rate. in fifo mode (16550): the break interrupt bit in the receiver fi fo will be copied to this register bit when its associated character is at the top of the receiver fifo. this bit is reset to ?0? when read. 3 0 ro urfe uart framing error in character mode (16450): when set, the received character does not have the correct stop bit.( ?0? is sampled) in fifo mode (16550): the framing error bit in the receiver fifo will be copied to this register bit when its associated character is at the top of the receiver fifo. this bit reset to ?0? when read. 2 0 ro urpe uart parity error in character mode (16450): when set, the received character does not have the correct even or odd parity (excluding stick parity), as sele cted by the parity select bit. in fifo mode (16550): the parity error bit in the receiver fifo will be copied to this register bit when its associated character is at t he top of the receiver fifo. this bit reset to ?0? when read. 1 0 ro urroe uart receive overrun error in character mode (16450): when set, the receive buffer register (rbr) has not been read by the cpu before the next character is ready to be transferred into rbr from the receive shift register. in fifo mode (16550): the receiver fifo is full and the next character is ready to be transferred into fifo from the receive shift register. this bit reset to ?0? when read. 0 0 ro urdr uart receive data ready in character mode (16450): when set, data is valid in the receive buffer register. in fifo mode (16550): there is at least one character data ready in the receive fifo (not empty.) this bit will be cleared when no data in receive buffer register or fifo.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 183 m9999-031810-1.2 2.19.25 uart 1 modem status register (ur1ms offset 0xe018) 2.19.26 uart 2 modem status register (ur2ms offset 0xe098) 2.19.27 uart 3 modem status register (ur3ms offset 0xe118) 2.19.28 uart 4 modem status register (ur4ms offset 0xe198) this register provides the current stat e of the modem input control lines to t he cpu. in addition to the current-state information, four bits of the modem st atus register provide state-changing inform ation. these bits are set to logic ?1? whenever a control input from the remote modem changes st ate. they are reset to ?0 ? whenever the cpu reads the register. when either one of the four bits urls[3:0] is set to ?1?, a modem status interrupt is generated. the following table shows the register bit fields. bit field default value read/ write description 31:8 0 ro reserved 7 -- ro urdcd uart data carrier detect this bit indicates the logical (inverted) value of the udcdn input. 6 -- ro urri uart ring indicator this bit indicates the logical (inver ted) value of t he urin input pin. 5 -- ro urdsr uart data set ready this bit indicates the logical (inver ted) value of the udsrn input pin. 4 -- ro urcts uart clear to send this bit indicates the logical (inver ted) value of the uctsn input pin. 3 0 ro urddcd uart delta data carrier detect this bit is set when the udcdn input pin has changed state. cleared when read. 2 0 ro urteri uart trailing edge ring indicator this bit is set when the urin input pin has changed from low to high. cleared when read. 1 0 ro urddst uart delta data set ready this bit is set when the uds rn input pin has changed state. cleared when read. 0 0 ro urdcts uart delta clear to send this bit is set when the uctsn input pin has changed state. cleared when read. 2.19.29 uart 1 baud rate divisor register (ur1bd offset 0xe01c) 2.19.30 uart 2 baud rate divisor register (ur2bd offset 0xe09c) 2.19.31 uart 3 baud rate divisor register (ur3bd offset 0xe11c) 2.19.32 uart 4 baud rate divisor register (ur4bd offset 0xe19c) the input clock to the baud rate generator is selected by urclksel. this clock is divided by the value in the urbd register to generate the sample clock (fsample), which is us ed to sample the incoming data or to drive the outgoing data. the frequency of frclk is 16 times of fsample.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 184 m9999-031810-1.2 the following table shows the register bit fields. bit field default value read/ write description 31:27 0x0 ro reserved 26:0 0x1be rw urbdc uart baud rate divisor count 2.19.33 uart 1 status register (us1r offset 0xe020) 2.19.34 uart 2 status register (us2r offset 0xe0a0) 2.19.35 uart 3 status register (us3r offset 0xe120) 2.19.36 uart 4 status register (us4r offset 0xe1a0) this register currently holds the tim eout indication bit. the timeout and receiv e triggered-level reach shares the same interrupt status(intst[9]) bit. to further distinguish these two interrupt sources, a timeout indication bit is introduced. the following table shows the register bit fields. bit field default value read/ write description 31:1 0x0 ro reserved 0 0 ro uti uart timeout indication bit if intst[9] = 1 and usr[0] = 1, the interrupt source is from timeout. if intst[9] = 1 and usr[0] = 0, the interr upt source is because the receive fifo has reached the trigger-level. note that this bit will be automatically cleared when either a new coming frame has received or cpu reads receive fifo. 2.20 interrupt controller registers the ksz8692mpb/KSZ8692XPB supports multiple interrupt sources with reconfigurable priority. interrupt requests can be generated by internal functional blocks as well as external pins. the arm core recognizes two kinds of interrupts: a normal interrupt request (irq), and a fast interrupt request (fiq ). all interrupts can be categor ized as either irq or fiq. the ksz8692mpb/KSZ8692XPB interrupt controller has an interrupt st atus bit for each interrupt source. this register defines the interrupt source for each device interrupt. in general, four special registers are used to control interrupt generation and handling: ? interrupt mode control register: defines the in terrupt source to the arm core, irq or fiq. ? interrupt priority register: the index number of each in terrupt source is written to the pre-defined interrupt priority register field to obtain the priority. t he interrupt priorities are predefined from 0 to 15. ? interrupt status register: i ndicates the interrupt status. ? interrupt enable register: enables the interrupts.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 185 m9999-031810-1.2 2.20.1 interrupt mode control register (intmc offset 0xe200) the following table shows the register bit fields. bit field default value read/ write description 31 0 ro reserved 30 0 rw wmtim wan mac transmit interrupt mode when set, the wan mac transmit interrupt corresponds to the fiq (fast interrupt). when reset, the wan mac transmit interrupt corresponds to the irq (normal interrupt). 29 0 rw wmrim wan mac receive interrupt mode when set, the wan mac receive interrupt corresponds to the fiq (fast interrupt). when reset, the wan mac receive interr upt corresponds to the irq (normal interrupt). 28 0 rw wmtbuim wan mac transmit buffer unavailable interrupt mode when set, the wan mac transmit buffer u navailable interrupt corresponds to the fiq (fast interrupt). when reset, the wan mac transmit buffer unavailable interrupt corresponds to the irq (normal interrupt). 27 0 rw wmrbuim wan mac receive buffer unavailable interrupt mode when set, the wan mac receive buffer unav ailable interrupt corresponds to the fiq (fast interrupt). when reset, the wan mac receive buffer unavailable interrupt corresponds to the irq (normal interrupt). 26 0 rw wmtpsim wan mac transmit process stopped interrupt mode when set, the wan mac transmit process stopped interrupt corresponds to the fiq (fast interrupt). when reset, the wan mac transmit process stopped interrupt corresponds to the irq (normal interrupt). 25 0 rw wmrpsim wan mac receive process stopped interrupt mode when set, the wan mac receive proce ss stopped interrupt corresponds to the fiq (fast interrupt). when reset, the wan mac receive process stopped interrupt corresponds to the irq (normal interrupt). 24 0 rw aberim amba bus error response interrupt mode when set, the amba bus error response interrupt corresponds to the fiq (fast interrupt). when reset, the amba bus error respons e interrupt corresponds to the irq (normal interrupt). 23:20 0x0 ro reserved 19 0 rw wwum wan wake-up interrupt mode when set, the wan wake-up interrupt corre sponds to the fiq (fast interrupt). when reset, the wan wake-up interrupt corresponds to the irq (normal interrupt). 18 0 rw lwum lan wake-up interrupt mode when set, the lan wake-up interrupt corre sponds to the fiq (fast interrupt). when reset, the lan wake-up interrupt corresponds to the irq (normal interrupt).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 186 m9999-031810-1.2 17 0 rw lmtim lan mac transmit interrupt mode when set, the lan mac transmit interrupt corresponds to the fiq (fast interrupt). when reset, the lan mac transmit interr upt corresponds to the irq (normal interrupt). 16 0 rw lmrim lan mac receive interrupt mode when set, the lan mac receive interrupt corresponds to the fiq (fast interrupt). when reset, the lan mac receive interr upt corresponds to the irq (normal interrupt). 15 0 rw lmtbuim lan mac transmit buffer unavailable interrupt mode when set, the lan mac transmit buffer unav ailable interrupt corresponds to the fiq (fast interrupt). when reset, the lan mac transmit buffer unavailable interrupt corresponds to the irq (normal interrupt). 14 0 rw lmrbuim lan mac receive buffer unavailable interrupt mode when set, the lan mac receive buffer unav ailable interrupt corresponds to the fiq (fast interrupt). when reset, the lan mac receive buffer unavailable interrupt corresponds to the irq (normal interrupt). 13 0 rw lmtpsim lan mac transmit process stopped interrupt mode when set, the lan mac transmit proce ss stopped interrupt corresponds to the fiq (fast interrupt). when reset, the lan mac transmit process stopped interrupt corresponds to the irq (normal interrupt). 12 0 rw lmrpsim lan mac receiv e process stopped interrupt mode when set, the lan mac receive proce ss stopped interrupt corresponds to the fiq (fast interrupt). when reset, the lan mac receive proce ss stopped interrupt corresponds to the irq (normal interrupt). 11 0 ro reserved 10 0 rw udim usb device interrupt mode when set, the usb device interrupt corre sponds to the fiq (fast interrupt). when reset, the usb device interrupt corresponds to the irq (normal interrupt). 9 0 rw uhoim usb host ohci interrupt mode when set, the usb host ohci interrupt co rresponds to the fiq (fast interrupt). when reset, the usb host ohci interr upt corresponds to the irq (normal interrupt). 8 0 rw uheim usb host ehci interrupt mode when set, the usb host ehci interrupt co rresponds to the fiq (fast interrupt). when reset, the usb host ehci interr upt corresponds to the irq (normal interrupt). 7 0 rw sdiom sdio interrupt mode when set, the sdio interrupt corresponds to the fiq (fast interrupt). when reset, the sdio interrupt corresponds to the irq (normal interrupt). 6 0 rw factory reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 187 m9999-031810-1.2 5 0 ro reserved 4 0 rw ddrim ddr error interrupt mode when set, the ddr interrupt corresponds to the fiq (fast interrupt). when reset, the ddr interrupt corresponds to the irq (normal interrupt). 3:0 0 ro reserved 2.20.2 interrupt mode control register2 (intmc2 offset 0xe204) the following table shows the register bit fields. bit field default value read/ write description 31:26 0x000 ro reserved 25 0 rw u4lseim uart4 line status error interrupt mode when set, the uart4 line status error in terrupt corresponds to the fiq (fast interrupt). when reset, the uart4 line status erro r interrupt corresponds to the irq (normal interrupt). 24 0 rw u4rtlrim uart4 receiver trigger level reached interrupt mode when set, the uart4 receiver trigger level reached interrupt corresponds to the fiq (fast interrupt). when reset, the uart4 receiver trigger level reached interrupt corresponds to the irq (normal interrupt). 23 0 rw u4teim uart4 transmitter empty interrupt mode when set, the uart4 transmitter empty interrupt corresponds to the fiq (fastl interrupt). when reset, the uart4 transmitter empty interrupt corresponds to the irq (normal interrupt). 22 0 rw u3lseim uart3 line status error interrupt mode when set, the uart3 line status error in terrupt corresponds to the fiq (fast interrupt). when reset, the uart3 line status erro r interrupt corresponds to the irq (normal interrupt). 21 0 rw u3rtlrim uart3 receiver trigger level reached interrupt mode when set, the uart3 receiver trigger level reached interrupt corresponds to the fiq (fast interrupt). when reset, the uart3 receiver trigger level reached interrupt corresponds to the irq (normal interrupt). 20 0 rw u3teim uart3 transmitter empty interrupt mode when set, the uart3 transmitter empty interrupt corresponds to the fiq (fast interrupt). when reset, the uart3 transmitter empty interrupt corresponds to the irq (normal interrupt). 19 0 rw u2lseim uart2 line status error interrupt mode when set, the uart2 line status error in terrupt corresponds to the fiq (fast interrupt). when reset, the uart2 line status erro r interrupt corresponds to the irq (normal interrupt).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 188 m9999-031810-1.2 18 0 rw u2rtlrim uart2 receiver trigger level reached interrupt mode when set, the uart2 receiver trigger level reached interrupt corresponds to the fiq (fast interrupt). when reset, the uart2 receiver trigger level reached interrupt corresponds to the irq (normal interrupt). 17 0 rw u2teim uart2 transmitter empty interrupt mode when set, the uart2 transmitter empty in terrupt corresponds to the fiq (fast interrupt). when reset, the uart2 transmitter empty interrupt corresponds to the irq (normal interrupt). 16 0 rw u1mim uart1 modem interrupt mode when set, the uart modem interrupt corre sponds to the fiq (fast interrupt). when reset, the uart modem interrupt corresponds to the irq (normal interrupt). 15 0 rw u1lseim uart1 line status error interrupt mode when set, the uart1 line status error in terrupt corresponds to the fiq (fast interrupt). when reset, the uart1 line status erro r interrupt corresponds to the irq (normal interrupt). 14 0 rw u1rtlrim uart1 receiver trigger level reached interrupt mode when set, the uart1 receiver trigger level reached interrupt corresponds to the fiq (fast interrupt). when reset, the uart1 receiver trigger level reached interrupt corresponds to the irq (normal interrupt). 13 0 rw u1teim uart1 transmitter empty interrupt mode when set, the uart1 transmitter empty in terrupt corresponds to the fiq (fast interrupt). when reset, the uart1 transmitter empty interrupt corresponds to the irq (normal interrupt). 12 0 rw mdiom mdio interrupt mode when set, the mdio interrupt corresponds to the fiq (fast interrupt). when reset, the mdio interrupt corresponds to the irq (normal interrupt). 11 0 rw spim spi interrupt mode when set, the spi interrupt corresponds to the fiq (fast interrupt). when reset, the spi interrupt corresponds to the irq (normal interrupt). 10 0 rw i2stm i2s transmit interrupt mode when set, the i2s transmit interrupt corre sponds to the fiq (fast interrupt). when reset, the i2s transmit interrupt co rresponds to the irq (normal interrupt). 9 0 rw i2srm i2s receive interrupt mode when set, the i2s receive interrupt corre sponds to the fiq (fast interrupt). when reset, the i2s receive interrupt corre sponds to the irq (normal interrupt). 8 0 rw i2cm i2c interrupt mode when set, the i2c interrupt corresponds to the fiq (fast interrupt). when reset, the i2c interrupt corresponds to the irq (normal interrupt). 7 0 rw t1im timer 1 interrupt mode when set, the timer 1 interrupt corres ponds to the fiq (fast interrupt). when reset, the timer 1 interrupt corresponds to the irq (normal interrupt).
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 189 m9999-031810-1.2 6 0 rw t0im timer 0 interrupt mode when set, the timer 0 interrupt corres ponds to the fiq (fast interrupt). when reset, the timer 0 interrupt corresponds to the irq (normal interrupt). 5 0 rw exti3m external interrupt 3 mode when set, the external interrupt 3 corre sponds to the fiq (fast interrupt). when reset, the external interrupt 3 corre sponds to the irq (normal interrupt). 4 0 rw exti2m external interrupt 2 mode when set, the external interrupt 2 corre sponds to the fiq (fast interrupt). when reset, the external interrupt 2 corre sponds to the irq (normal interrupt). 3 0 rw exti1m external interrupt 1 mode when set, the external interrupt 1 corre sponds to the fiq (fast interrupt). when reset, the external interrupt 1 corre sponds to the irq (normal interrupt). 2 0 rw exti0m external interrupt 0 mode when set, the external interrupt 0 corre sponds to the fiq (fast interrupt). when reset, the external interrupt 0 corre sponds to the irq (normal interrupt). 1 0 rw cctm communications channel transmit mode when set, the communications channel transmit corresponds to the fiq (fast interrupt). when reset, the communications channel transmit corresponds to the irq (normal interrupt). 0 0 rw ccrm communications channel receive mode when set, the communications channel receive corresponds to the fiq (fast interrupt). when reset, the communications channel re ceive corresponds to the irq (normal interrupt). 2.20.3 interrupt enable register (inten offset 0xe208) this register enables the interrupts from the internal or external sources. the following table shows the register bit fields. bit field default value read/ write description 31 0 ro reserved 30 0 rw wmtie wan mac transmit interrupt enable when this bit is set, the wan mac transmit interrupt is enabled. when this bit is reset, the wan mac transmit interrupt is disabled. 29 0 rw wmrie wan mac receive interrupt enable when this bit is set, the wan mac receive interrupt is enabled. when this bit is reset, the wan mac receive interrupt is disabled. 28 0 rw wmtbuie wan mac transmit buffer unavailable interrupt enable when this bit is set, the wan mac transmit buffer unavailable interrupt is enabled. when this bit is reset, the wan mac tr ansmit buffer unavailable interrupt is disabled. 27 0 rw wmrbuie wan mac receive buffer unavailable interrupt enable when this bit is set, the wan mac receiv e buffer unavailable interrupt is enabled. when this bit is reset, the wan mac receiv e buffer unavailable interrupt is disabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 190 m9999-031810-1.2 26 0 rw wmtpsie wan mac transmit process stopped interrupt enable when this bit is set, the wan mac transmit process stopped interrupt is enabled. when this bit is reset, the wan mac transmit process stopped interrupt is disabled. 25 0 rw wmrpsie wan mac receive process stopped interrupt enable when this bit is set, the wan mac receive process stopped interrupt is enabled. when this bit is reset, the wan mac receive process stopped interrupt is disabled. 24 0 rw aberie amba bus error response interrupt enable when this bit is set, the amba bus error response interrupt is enabled. when this bit is reset, the amba bus e rror response interrupt is disabled. 23:20 0x0 ro reserved 19 0 rw wwuie wan wake-up interrupt enable when set, the wan wake-up interrupt is enabled. when reset, the wan wake-up interrupt is disabled. 18 0 rw lwuie lan wake-up interrupt enable when set, the lan wake-up interrupt is enabled. when reset, the lan wake-up interrupt is disabled 17 0 rw lmtie lan mac transmit interrupt enable when set, the lan mac transmit interrupt is enabled. when reset, the lan mac transmit interrupt is disabled. 16 0 rw lmrie lan mac receive interrupt enable when set, the lan mac receive interrupt is enabled. when reset, the lan mac receive interrupt is disabled. 15 0 rw lmtbuie lan mac transmit buffer unavailable interrupt enable when set, the lan mac transmit buffer unavailable interrupt is enabled. when reset, the lan mac transmit buffer unavailable interrupt is disabled. 14 0 rw lmrbuie lan mac receive buffer unavailable interrupt enable when set, the lan mac receive buffer unavailable interrupt is enabled. when reset, the lan mac receive buffer unavailable interrupt is disabled. 13 0 rw lmtpsie lan mac transmit process stopped interrupt enable when set, the lan mac transmit process stopped interrupt is enabled. when reset, the lan mac transmit process stopped interrupt is disabled. 12 0 rw lmrpsie lan mac receiv e process stopped interrupt enable when set, the lan mac receive pr ocess stopped interrupt is enabled. when reset, the lan mac receive proc ess stopped interrupt is disabled. 11 0 ro reserved 10 0 rw udie usb device interrupt enable when set, the usb device interrupt is enabled. when reset, the usb device interrupt is disabled. 9 0 rw uhoie usb host ohci interrupt enable when set, the usb host ohci interrupt is enabled. when reset, the usb host ohci interrupt is disabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 191 m9999-031810-1.2 8 0 rw uheie usb host ehci interrupt enable when set, the usb host ehci interrupt is enabled. when reset, the usb host ehci interrupt is disabled. 7 0 rw sdioie sdio interrupt enable when set, the sdio interrupt is enabled. when reset, the sdio interrupt is disabled. 6 0 rw factory reserved 5 0 ro reserved 4 0 rw ddrie ddr error interrupt enable when set, the ddr interrupt is enabled. when reset, the ddr interrupt is disabled. 3:0 0 ro reserved 2.20.4 interrupt enable register2 (inten2 offset 0xe20c) the following table shows the register bit fields. bit field default value read/ write description 31:26 0x000 ro reserved. 25 0 rw u4lsee uart4 line status error enable when set, the uart4 line status error interrupt is enabled. when reset, the uart4 line status error interrupt is disabled. 24 0 rw u4rtlre uart4 receiver trigger level reached enable when set, the uart4 receiver trigger level reached interrupt is enabled. when reset, the uart4 receiver trigger level reached interrupt is disabled. 23 0 rw u4tee uart4 transmitter empty enable when set, the uart4 transmitter empty interrupt corresponds to the fiq (fastl interrupt). when reset, the uart4 transmitter empty interrupt is disabled. 22 0 rw u3lsee uart3 line status error enable when set, the uart3 line status error interrupt is enabled. when reset, the uart3 line status error interrupt is disabled. 21 0 rw u3rtlre uart3 receiver trigger level reached enable when set, the uart3 receiver trigger level reached interrupt is enabled. when reset, the uart3 receiver trigger level reached interrupt is disabled. 20 0 rw u3tee uart3 transmitter empty enable when set, the uart3 transmitter empty interrupt is enabled. when reset, the uart3 transmitter empty interrupt is disabled. 19 0 rw u2lsee uart2 line status error enable when set, the uart2 line status error interrupt is enabled. when reset, the uart2 line status error interrupt is disabled. 18 0 rw u2rtlre uart2 receiver trigger level reached enable when set, the uart2 receiver trigger level reached interrupt is enabled. when reset, the uart2 receiver trigger level reached interrupt is disabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 192 m9999-031810-1.2 17 0 rw u2tee uart2 transmitter empty enable when set, the uart2 transmitter empty interrupt is enabled. when reset, the uart2 transmitter empty interrupt is disabled. 16 0 rw u1me uart1 modem enable when set, the uart modem interrupt is enabled. when reset, the uart modem interrupt is disabled. 15 0 rw u1lsee uart1 line status error enable when set, the uart1 line status error interrupt is enabled. when reset, the uart1 line status error interrupt is disabled. 14 0 rw u1rtlre uart1 receiver trigger level reached enable when set, the uart1 receiver trigger level reached interrupt is enabled. when reset, the uart1 receiver trigger level reached interrupt is disabled. 13 0 rw u1tee uart1 transmitter empty enable when set, the uart1 transmitter empty interrupt is enabled. when reset, the uart1 transmitter empty interrupt is disabled. 12 0 rw mdioe mdio enable when set, the mdio interrupt is enabled. when reset, the mdio interrupt is disabled. 11 0 rw spie spi enable when set, the spi interrupt is enabled. when reset, the spi interrupt is disabled. 10 0 rw i2ste i2s transmit enable when set, the i2s transmit interrupt is enabled. when reset, the i2s transmit interrupt corre sponds to the irq (normalt interrupt). 9 0 rw i2sre i2s receive enable when set, the i2s receive interrupt is enabled. when reset, the i2s receive interrupt is disabled. 8 0 rw i2ce i2c enable when set, the i2c interrupt is enabled. when reset, the i2c interrupt is disabled. 7 0 rw t1ie timer 1 enable when set, the timer 1 interrupt is enabled. when reset, the timer 1 interrupt is disabled. 6 0 rw t0ie timer 0 enable when set, the timer 0 interrupt is enabled. when reset, the timer 0 interrupt is disabled. 5 0 rw exti3e external interrupt 3 enable when set, the external interrupt 3 is enabled. when reset, the external interrupt 3 is disabled. 4 0 rw exti2e external interrupt 2 enable when set, the external interrupt 2 is enabled. when reset, the external interrupt 2 is disabled. 3 0 rw exti1e external interrupt 1 enable when set, the external interrupt 1 is enabled. when reset, the external interrupt 1 is disabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 193 m9999-031810-1.2 2 0 rw exti0e external interrupt 0 enable when set, the external interrupt 0 is enabled. when reset, the external interrupt 0 is disabled. 1 0 rw ccte communications channel transmit enable when set, the communications channel transmit is enabled. when reset, the communications channel transmit is disabled. 0 0 rw ccre communications channel receive enable when set, the communications channel receive is enabled. when reset, the communications channel receive is disabled. 2.20.5 interrupt status register (intst offset 0xe210) this register contains all the status bits for the arm cpu. when corresponding enable bit is set, it cause the cpu to be interrupted. this register is usually read by the driver during interrupt service r outine or polling. the register bits are no t cleared when read. each field can be masked. the following table shows the register bit fields. bit field default value read/ write description 31 0 ro reserved 30 0 rw wmts wan mac transmit status when this bit is set, it indicates that the wan mac has transmitted at least a frame on the wan port and the mac is r eady for new frames from the host. this edge-triggered interrupt status is cleared by writing 1 to this bit. 29 0 rw wmrs wan mac receive status when this bit is set, it indicates that the wan mac has received a frame from the wan port and it is ready for the host to process this edge-triggered interrupt status is cleared by writing 1 to this bit. 28 0 rw wmtbus wan mac transmit buffer unavailable status when this bit is set, it indicates that the next descriptor on the transmit list is owned by the host and cannnot be ac quired by the ksz8692mpb/KSZ8692XPB. the transmission process is suspended. to resume processing transmit descriptors, the host should change the ow nership bit of the descriptor and then issue a transmit start command. this edge-triggered interrupt status is cleared by writing 1 to this bit. 27 0 rw wmrbus wan mac receive buffer unavailable status when this bit is set, it indicates that the descriptor list is owned by the host and cannot be acquired by the ksz8692mpb/ksz 8692xpb. the receiving process is suspended. to resume processing receive descriptors, the host should change the ownership of the descriptor and ma y issue a receive start command. if no receive start command is issued, the re ceiving process resumes when the next recognized incoming frame is received. afte r the first assertion, this bit is not asserted for any subsequent not owned receive descriptors fetches. this bit is asserted only when the previous receive descriptor was owned by the ksz8692mpb/KSZ8692XPB. this edge-triggered interrupt status is cleared by writing 1 to this bit. 26 0 rw wmtpss wan mac transmit process stopped status asserted when the wan mac transmit process enters t he stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 25 0 rw wmrpss wan mac receive process stopped status asserted when the wan mac receive process enters t he stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 194 m9999-031810-1.2 24 0 ro abers amba bus error response status when this bit is set, it indicates that either wan or lan amba master has received a bus error response from slave(memory controller). this level-triggered interrupt status is automatically cleared when interrupt source is cleared. 23:20 0x0 ro reserved 19 0 rw wwum wan wake-up status when set, the wan wake-up interrupt is enabled. when reset, the wan wake-up interrupt is disabled. this status is cleared by writing 1 to this bit. 18 0 rw lwum lan wake-up interrupt enable when set, the lan wake-up interrupt is enabled. when reset, the lan wake-up interrupt is disabled. this status is cleared by writing 1 to this bit. 17 0 rw lmts lan mac transmit status when this bit is set, it indicates that the lan mac has transmitted at least a frame on the lan port and the mac is r eady for new frames from the host. this edge-triggered interrupt status is cleared by writing 1 to this bit. 16 0 rw lmrs lan mac receive status when this bit is set, it indicates that the lan mac has received a frame from the lan port and it is ready for the host to process this edge-triggered interrupt status is cleared by writing 1 to this bit. 15 0 rw lmtbus lan mac transmit buffer unavailable status when this bit is set, it indicates that the next descriptor on the transmit list is owned by the host and cannnot be ac quired by the ksz8692mpb/KSZ8692XPB. the transmission process is suspended. to resume processing transmit descriptors, the host should change the ow nership bit of the descriptor and then issue a transmit start command. this edge-triggered interrupt status is cleared by writing 1 to this bit. 14 0 rw lmrbus lan mac receive buffer unavailable status when this bit is set, it indicates that the descriptor list is owned by the host and cannot be acquired by the ksz8692mpb/ksz 8692xpb. the receiving process is suspended. to resume processing receive descriptors, the host should change the ownership of the descriptor and ma y issue a receive start command. if no receive start command is issued, the re ceiving process resumes when the next recognized incoming frame is received. afte r the first assertion, this bit is not asserted for any subsequent not owned receive descriptors fetches. this bit is asserted only when the previous receive descriptor was owned by the ksz8692mpb/KSZ8692XPB. this edge-triggered interrupt status is cleared by writing 1 to this bit. 13 0 rw lmtpss lan mac trans mit process stopped status asserted when the lan mac transmit process enters t he stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 12 0 rw lmrpss lan mac rece ive process stopped status asserted when the lan mac receive process enters t he stopped state. this edge-triggered interrupt status is cleared by writing 1 to this bit. 11 0 ro reserved 10 0 rw udis usb device interrupt status this level-triggered interrupt status is automatically cleared when interrupt source is cleared. please refer usb register section.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 195 m9999-031810-1.2 9 0 rw uhois usb host ohci interrupt status this level-triggered interrupt status is automatically cleared when interrupt source is cleared. please refer usb register section. 8 0 rw uheis usb host ehci interrupt status this level-triggered interrupt status is automatically cleared when interrupt source is cleared. please refer usb register section. 7 0 ro sdios sdio status when this bit is set, it indicates t hat sdio module has detected an interrrupt event. this level-triggered interrupt status is automatically cleared when interrupt source is cleared. please refer sdio register section. 6 0 ro factory reserved 5 0 ro reserved 4 0 ro ddrs ddr error interrupt status when this bit is set, it indicates that ddr controller has detected an error event. this level-triggered interrupt status is automatically cleared when interrupt source is cleared. 3:0 0x0 ro reserved 2.20.6 interrupt status register2 (inst2 offset 0xe214) the following table shows the register bit fields. bit field default value read/ write description 31:26 0x000 ro reserved. 25 0 rw uart4 line status error interrupt status 24 0 rw uart4 receiver trigger level reached interrupt status 23 0 rw uart4 transmitter empty interrupt status 22 0 rw uart3 line status error interrupt status 21 0 rw uart3 receiver trigger level reached interrupt status 20 0 rw uart3 transmitter empty interrupt status 19 0 rw uart2 line status error interrupt status 18 0 rw uart2 receiver trigger level reached interrupt status 17 0 rw uart2 transmitter empty interrupt status 16 0 ro uart1 modem interrupt status when this bit is set, it indicates that the uart modem status is set. uart modem status is defined as logic or of delta data carrier detect, trailing edge ring indicator, delta data set ready and delta clear to send. this level-triggered interrupt status is automatically cleared when uart modem status register is read. 15 0 ro uart1 line status error interrupt status when this bit is set, it indicates that the uart line error status is set. uart line error status is defined as l ogic or of the following line conditions: overrun error, parity error, fr aming error, break interrupt. this level-triggered interrupt status is automatically cleared when uart line status register is read.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 196 m9999-031810-1.2 14 0 ro uart1 receiver trigger level reached interrupt status when this bit is set, it indicates t hat the uart receive status is set. uart receive status is defined as l ogic or of received data available or character timeout indication. for received data available, it indicates receive buffer register is full(character mode) or trigger-level reached(fifo mode). this level-triggered interrupt status is automatically cleared when uart receive buffer register is read or fifo drops below trigger-level. for character timeout indication, it indicates timeout has occured in fifo mode. this level-triggered interrupt status is automatically cleared when cpu reads a datum back. note that uart status register can provide further information if this interrupt status is for received data available or timeout. 13 0 rw uart1 transmitter empty interrupt status when this bit is set, it indicates that the uart transmit status is set. uart transmit status is defined as the emptiness of transmit holding register. this edge-triggered interrupt status is cleared by writing 1 to this bit. 12 0 rw mdiois mdio interrupt status 11 0 rw spiis spi interrupt status 10 0 rw i2stis i2s transmit interrupt status 9 0 rw i2sris i2s receive interrupt status 8 0 rw i2cis i2s interrupt status indicates one of the interrupt conditi ons have been triggered. check the i2c status register to determine the cause of the interrupt. 7 0 rw t1ms timer 1 status when this bit is set, it indicates that the timer 1 status is set as specified in the timer 1 registers. this edge-triggered interrupt status is cleared by writing 1 to this bit. 6 0 rw t0ms timer 0 status when this bit is set, it indicates that the timer 0 status is set as specified in the timer 0 registers. this edge-triggered interrupt status is cleared by writing 1 to this bit. 5 0 rw exti3s external interrupt 3 status when this bit is set, it indicates that the external interrupt 3 pin is set. this interrupt status is cleared by writing 1 to this bit if edge-trigger is selected. 4 0 rw exti2s external interrupt 2 status when this bit is set, it indicates that the external interrupt 2 pin is set. this interrupt status is cleared by writing 1 to this bit if edge-trigger is selected. 3 0 rw exti1s external interrupt 1 status when this bit is set, it indicates that the external interrupt 1 pin is set. this interrupt status is cleared by writing 1 to this bit if edge-trigger is selected.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 197 m9999-031810-1.2 2 0 rw exti0s external interrupt 0 status when this bit is set, it indicates that the external interrupt 0 pin is set. this interrupt status is cleared by writing 1 to this bit if edge-trigger is selected. 1 0 ro ccts communications channel transmit status. when this bit is set, it indicates that the communications channel transmit pin is set. when high, this signal denotes that the comms channel transmit buffer is empty. this level-triggered interrupt status is automatically cleared when interrupt source is cleared. 0 0 ro ccrs communications channel receive status. when this bit is set, it indicates that the communications channel receive pin is set. when high, this signal denotes that the comms channel receive buffer contains data waiting to be read by the processor core. this level-triggered interrupt status is automatically cleared when interrupt source is cleared. 2.20.7 interrupt priority register for wan mac (intpw offset 0xe218) this register configures the priority of the wan dma interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:28 0x0 ro reserved 27:24 0x0 rw wmtip wan mac transmit interrupt priority level this field defines the priority level of the wan mac transmit interrupt if enabled. 23:20 0x0 rw wmrip wan mac receive interrupt priority level this field defines the priority level of the wan mac receive interrupt if enabled. 19:16 0x0 rw wmtbuip wan mac transmit buffe r unavailable interrupt priority level this field defines the priority level of the wan mac transmit buffer unavailable interrupt if enabled. 15:12 0x0 rw wmtbuip wan mac receive buffer unavailable interrupt priority level this field defines the priority level of the wan mac receive buffer unavailable interrupt if enabled. 11:8 0x0 rw wmtpsip wan mac transmit pr ocess stopped interrupt priority level this field defines the priority leve l of the wan mac transmit process stopped interrupt if enabled. 7:4 0x0 rw wmrpsip wan mac receive pr ocess stopped interrupt priority level this field defines the priority leve l of the wan mac receive process stopped interrupt if enabled. 3:0 0x0 rw wwipl wan wake-up interrupt priority level this field defines the priority level of the wan wake-up interrupt if enabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 198 m9999-031810-1.2 2.20.8 interrupt priority register for bus error response (intpbe offset 0xe21c) the following table shows the register bit fields. bit field default value read/ write description 31:4 0x0 ro reserved 3:0 0x0 rw aberp amba bus error response priority level this field defines the priority leve l of the bus error response if enabled. 2.20.9 interrupt priority register for lan mac (intpl offset 0xe220) this register configures the priority of the lan dma interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:28 0x0 rw reserved. 27:24 0x0 rw lmtip lan mac transmit interrupt priority level this field defines the priority level of the lan mac transmit interrupt if enabled. 23:20 0x0 rw lmrip lan mac receive interrupt priority level this field defines the priority level of the lan mac receive interrupt if enabled. 19:16 0x0 rw lmtbuip lan mac transmit buffe r unavailable interrupt priority level this field defines the priority level of the lan mac transmit buffer unavailable interrupt if enabled. 15:12 0x0 rw lmtbuip lan mac receive buffe r unavailable interrupt priority level this field defines the priority level of the lan mac receive buffer unavailable interrupt if enabled. 11:8 0x0 rw lmtpsip lan mac transmit pr ocess stopped interrupt priority level this field defines the priority leve l of the lan mac transmit process stopped interrupt if enabled. 7:4 0x0 rw lmrpsip lan mac receive pr ocess stopped interrupt priority level this field defines the priority leve l of the lan mac receive process stopped interrupt if enabled. 3:0 0x0 rw lwipl lan wake-up interrupt priority level this field defines the priority level of the lan wake-up interrupt if enabled. 2.20.10 interrupt priority register for usb (intpusb offset 0xe224) this register configures the priority of the usb interrupt source. there are a tota l of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. note that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:12 0x0 ro reserved. 11:8 0x0 rw usbhep usb host ehci interrupt level 7:4 0x0 rw usbhop usb host ohci interrupt level 3:0 0x0 rw usbdp usb device interrupt priority level this field defines the priority level of the usb device interrupt if enabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 199 m9999-031810-1.2 2.20.11 interrupt priority register for sdio (intpsdio offset 0xe228) this register configures the priority of the sdio interrupt source. there are a to tal of 16 priority levels, 0xf has the highes t priority; 0x0 has the lowest priority. note that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:4 0x0 ro reserved. 3:0 0x0 rw sdiop sdio interrupt priority level this field defines the priority le vel of the sdio interrupt if enabled. 2.20.12 factory reserved (offset 0xe22c) 2.20.13 interrupt priority register for ddr (intpddr offset 0xe230) this register configures the priority of the ddr interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:4 0x0 ro reserved. 3:0 0x0 rw ddrp ddr interrupt priority level this field defines the priority level of the ddr interrupt if enabled. 2.20.14 interrupt priority register for uart (intpu offset 0xe234) this register configures the priority of the uart interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 27:24 0x0 rw u2lesip uart2 line error status interrupt priority level this field defines the priority level of the line error status interrupt if enabled. 23:20 0x0 rw u2rip uart2 receive interrupt priority level this field defines the priority level of the uart receive interrupt if enabled. 19:16 0x0 rw u2tip uart2 transmit interrupt priority level this field defines the priority level of the uart transmit interrupt if enabled. 15:12 0x0 rw msip modem status interrupt priority level this field defines the priority level of the modem status interrupt if enabled. 11:8 0x0 rw u1lesip uart1 line error status interrupt priority level this field defines the priority level of the line error status interrupt if enabled. 7:4 0x0 rw u1rip uart1 receive interrupt priority level this field defines the priority level of the uart receive interrupt if enabled. 3:0 0x0 rw u1tip uart1 transmit interrupt priority level this field defines the priority level of the uart transmit interrupt if enabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 200 m9999-031810-1.2 2.20.15 interrupt priority register2 for uart (intpu2 offset 0xe238) this register configures the priority of the uart interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:24 0x0 ro reserved 23:20 0x0 rw u4lesip uart4 line error status interrupt priority level this field defines the priority level of the line error status interrupt if enabled. 19:16 0x0 rw u4rip uart4 receive interrupt priority level this field defines the priority level of the uart receive interrupt if enabled. 15:12 0x0 rw u4tip uart4 transmit interrupt priority level this field defines the priority level of the uart transmit interrupt if enabled. 11:8 0x0 rw u3lesip uart3 line error status interrupt priority level this field defines the priority level of the line error status interrupt if enabled. 7:4 0x0 rw u3rip uart3 receive interrupt priority level this field defines the priority level of the uart receive interrupt if enabled. 3:0 0x0 rw u3tip uart3 transmit interrupt priority level this field defines the priority level of the uart transmit interrupt if enabled. 2.20.16 interrupt priority register for mdio (intpmdio offset 0xe23c) this register configures the priority of the mdio interrupt source. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:4 0x0 rw reserved. 3:0 0x0 rw mdiop mdio interrupt priority level this field defines the priority le vel of the mdio interrupt if enabled. 2.20.17 interrupt priority register for spi (intpspi offset 0xe240) this register configures the priority of the spi interrupt source. there are a tota l of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. note that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:4 0x0 rw reserved. 3:0 0x0 rw spip spi interrupt priority level this field defines the priority le vel of the spi interrupt if enabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 201 m9999-031810-1.2 2.20.18 interrupt priority register for i2s (intpi2s offset 0xe244) this register configures the priority of the i2s interrupt source. there are a tota l of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. note that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 rw reserved. 7:4 0x0 rw i2stp i2s transmit interrupt priority level this field defines the priority level of the i2s transmit interrupt if enabled. 3:0 0x0 rw i2srp i2s receiv e interrupt priority level this field defines the priority level of the i2s receive interrupt if enabled. 2.20.19 interrupt priority register for i2c (intpi2c offset 0xe248) this register configures the priority of the i2c interrupt source. there are a tota l of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. note that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:4 0x0 rw reserved. 3:0 0x0 rw i2cp i2c interrupt priority level this field defines the priority le vel of the i2c interrupt if enabled. 2.20.20 interrupt priority register for timer (intpt offset 0xe24c) this register configures the priority of the timer interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:4 0x0 rw t1ip timer 1 interrupt priority level this field defines the priority leve l of the timer 1 interrupt if enabled. 3:0 0x0 rw t0ip timer 0 interrupt priority level this field defines the priority leve l of the timer 0 interrupt in enabled. 2.20.21 interrupt priority register for external interrupt (intpe offset 0xe250) this register configures the priority of the external interrupt sources. there are a total of 16 priority levels, 0xf has the highest priority; 0x0 has the lowest priority. no te that fiq still has higher precedence over irq. the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 15:12 0x0 rw exti3p external interrupt 3 priority level this field defines the priority level of the external interrupt 3 if enabled.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 202 m9999-031810-1.2 11:8 0x0 rw exti2p external interrupt 2 priority level this field defines the priority level of the external interrupt 2 if enabled. 7:4 0x0 rw exti1p external interrupt 1 priority level this field defines the priority level of the external interrupt 1 if enabled. 3:0 0x0 rw exti0p external interrupt 0 priority level this field defines the priority level of the external interrupt 0 if enabled. 2.20.22 interrupt priority register for communications channel (intpc offset 0xe254) the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:4 0x0 rw cctp communications channel transmit priority level this field defines the priority level of the communications channel transmit if enabled. 3:0 0x0 rw ccrp communications channel receive priority level this field defines the priority level of the communications channel receive if enabled. 2.20.23 interrupt mask status register (intms offset 0xe258) this register is the logical and of the interrupt enable register and the interrupt sta tus register. this register is read only . the following table shows the register bit fields. bit field default value read/ write description 31 0 ro reserved 30 0 ro wmtims wan mac transmit interrupt mask status when this bit is set, it indicates that the wan mac transmit interrupt is enabled and its corresponding status bit is set. 29 0 ro wmrims wan mac receive interrupt mask status when this bit is set, it indicates that the wan mac receive interrupt is enabled and its corresponding status bit is set. 28 0 ro wmtbums wan mac transmit buffer unavailable interrupt mask status when this bit is set, it indicates that the wan mac transmit buffer unavailable interrupt is enabled and its corresponding status bit is set. 27 0 ro wmrbums wan mac receive buffer unavailable interrupt mask status when this bit is set, it indicates that the wan mac receive buffer unavailable interrupt is enabled and its corresponding status bit is set. 26 0 ro wmtpsms wan mac transmit process stopped interrupt mask status when this bit is set, it indicates that the wan mac transmit process stopped interrupt is enabled and its corresponding status bit is set. 25 0 ro wmrpsms wan mac receive process stopped interrupt mask status when this bit is set, it indicates t hat the wan mac receive process stopped interrupt is enabled and its corresponding status bit is set. 24 0 ro aberms amba bus error response interrupt mask status when this bit is set, it indicates that the amba bus error response interrupt is enabled and its corresponding status bit is set. 23:20 0x00 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 203 m9999-031810-1.2 19 0 ro wwums wan wake-up mask status when set, the wan wake-up interrupt is enabled and its corresponding status bit is set. 18 0 ro lwums lan wake-up mask status when set, the lan wake-up interrupt is enabled and its corresponding status bit is set. 17 0 ro lmtims lan mac transmit interrupt mask status when this bit is set, it indicates that the lan mac transmit interrupt is enabled and its corresponding status bit is set. 16 0 ro lmrims lan mac rece ive interrupt mask status when this bit is set, it indicates that the lan mac receive interrupt is enabled and its corresponding status bit is set. 15 0 ro lmtbums lan mac transmit buffe r unavailable interrupt mask status when this bit is set, it indicates that the lan mac transmit buffer unavailable interrupt is enabled and its corresponding status bit is set. 14 0 ro lmrbums lan mac receive buffe r unavailable interrupt mask status when this bit is set, it indicates that the lan mac receive buffer unavailable interrupt is enabled and its corresponding status bit is set. 13 0 ro lmtpsms lan mac transmit pr ocess stopped interrupt mask status when this bit is set, it indicates t hat the lan mac transmit process stopped interrupt is enabled and its corresponding status bit is set. 12 0 ro lmrpsms lan mac receive pr ocess stopped interrupt mask status when this bit is set, it indicates t hat the lan mac receive process stopped interrupt is enabled and its corresponding status bit is set. 11 0 ro reserved 10 0 rw udms usb device mask status when this bit is set, it indicates that usb device interrrupt is enabled and its corresponding status bit is set. 9 0 rw uhoms usb host ohci mask status when this bit is set, it indicates that usb host ohci interrrupt is enabled and its corresponding status bit is set. 8 0 rw uhems usb host ehci mask status when this bit is set, it indicates that usb host ehci interrrupt is enabled and its corresponding status bit is set. 7 0 ro sdioms sdio mask status when this bit is set, it indicates that sdio interrrupt is enabled and its corresponding status bit is set. 6 0 ro factory reserved 5 0 ro reserved 4 0 ro ddrms ddr mask status when this bit is set, it indicate s that ddr interrrupt is enabled and its corresponding status bit is set. 3:0 0 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 204 m9999-031810-1.2 2.20.24 interrupt mask register2 (intms2 offset 0xe25c) the following table shows the register bit fields. bit field default value read/ write description 31:26 0x000 ro reserved. 25 0 rw u4lsems uart4 line status error mask status when this bit is set, it indicates that the uart4 line status error interrupt is enabled and its corresponding status bit is set. 24 0 rw u4rtlrms uart4 receiver trigger level reached mask status when this bit is set, it indicates that the uart4 line receiver trigger level reached interrupt is enabled and its corresponding status bit is set. 23 0 rw u4tems uart4 transmitter empty mask status when this bit is set, it indicates that the uart4 transmitter empty interrupt is enabled and its corresponding status bit is set. 22 0 rw u3lsems uart3 line status error mask status when this bit is set, it indicates that the uart3 line status error interrupt is enabled and its corresponding status bit is set. 21 0 rw u3rtlrms uart3 receiver trigger level reached mask status when this bit is set, it indicates that the uart3 receiver trigger level reached interrupt is enabled and its corresponding status bit is set. 20 0 rw u3tems uart3 transmitter empty mask status when this bit is set, it indicates that the uart3 transmitter empty interrupt is enabled and its corresponding status bit is set. 19 0 rw u2lsems uart2 line status error mask status when this bit is set, it indicates that the uart2 line status error interrupt is enabled and its corresponding status bit is set. 18 0 rw u2rtlrms uart2 receiver trigger level reached mask status when this bit is set, it indicates that the uart2 receiver trigger level reached interrupt is enabled and its corresponding status bit is set. 17 0 rw u2tems uart2 transmitter empty mask status when this bit is set, it indicates that the uart2 transmitter empty interrupt is enabled and its corresponding status bit is set. 16 0 rw uart1mms uart modem mask status when this bit is set, it indicates that the uart modem interrupt is enabled and its corresponding status bit is set. 15 0 rw u1lsems uart1 line status error mask status when this bit is set, it indicates that the uart1 line status error interrupt is enabled and its corresponding status bit is set. uart line error status is defined as l ogic or of the following line conditions: overrun error, parity error, fr aming error, break interrupt. 14 0 rw u1rtlrms uart1 receiver trigger level reached mask status when this bit is set, it indicates that the uart1 line status error interrupt is enabled and its corresponding status bit is set. 13 0 rw u1tems uart1 transmitter empty mask status when this bit is set, it indicates that the uart1 transmitter empty interrupt is enabled and its corresponding status bit is set. 12 0 rw mdioms mdio mask status when this bit is set, it indicates t hat the mdio interrupt is enabled and its corresponding status bit is set.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 205 m9999-031810-1.2 11 0 rw spims spi mask status when this bit is set, it indicates t hat the spi interrupt is enabled and its corresponding status bit is set. 10 0 rw i2stms i2s transmit mask status when this bit is set, it indicates t hat the i2s interrupt is enabled and its corresponding status bit is set. 9 0 rw i2srms i2s receive mask status when this bit is set, it indicates that i2s interrupt is enabled and its corresponding status bit is set. 8 0 rw i2cms i2c mask status when this bit is set, it indicates t hat the i2c interrupt is enabled and its corresponding status bit is set. 7 0 ro t1ims timer 1 interrupt mask status when this bit is set, it indicates that the timer 1 interrupt is enabled and its corresponding status bit is set. 6 0 ro t0ims timer 0 interrupt mask status when this bit is set, it indicates that the timer 0 interrupt is enabled and its corresponding status bit is set. 5 0 ro exti3ms external interrupt 3 mask status when this bit is set, it indicates that the external interrupt 3 is enabled and its corresponding status bit is set. 4 0 ro exti2ms external interrupt 2 mask status when this bit is set, it indicates that the external interrupt 2 is enabled and its corresponding status bit is set. 3 0 ro exti1ms external interrupt 1 mask status when this bit is set, it indicates that the external interrupt 1 is enabled and its corresponding status bit is set. 2 0 ro exti0ms external interrupt 0 mask status when this bit is set, it indicates that the external interrupt 0 is enabled and its corresponding status bit is set. 1 0 ro cctms communications channel transmit mask status when this bit is set, it indicates that the communications channel transmit is enabled and its corresponding status bit is set. 0 0 ro ccrms communications channel receive mask status when this bit is set, it indicates that the communications channel receive is enabled and its corresponding status bit is set. 2.20.25 interrupt pending highest priority register for fiq (inthpf offset 0xe260) this register provides the interrupt in formation for the host to identify the pending interrupts with highest priority for fiq (fast interrupt) note that it is possible to have more t han one higest interrupts pending because of the same priority level. this register is provided to the host to quickly identify and serv ice the fiq interrupt with highes t priority. this register is read only. the following table shows the register bit fields. bit field default value read/ write description 31 0 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 206 m9999-031810-1.2 30 0 ro wmtipf wan mac transmit interrupt pending for fiq when this bit is set, it indicates that the wan mac transmit interrupt has the highest priority among all the fiq interrupts pending currently. 29 0 ro wmripf wan mac receive interrupt pending for fiq when this bit is set, it indicates that the wan mac receive interrupt has the highest priority among all the fiq interrupts pending currently. 28 0 ro wmtbuipf wan mac transmit buffer unavailable interrupt pending for fiq when this bit is set, it indicates that the wan mac transmit buffer unavailable interrupt has the highest priority among all the fiq interrupts pending currently. 27 0 ro wmrbuipf wan mac receivet buffer unavailable interrupt pending for fiq when this bit is set, it indicates that the wan mac receive buffer unavailable interrupt has the highest priority among all the fiq interrupts pending currently. 26 0 ro wmtpsipf wan mac transmit process stopped interrupt pending for fiq when this bit is set, it indicates that the wan mac transmit process stopped interrupt has the highest priority among all the fiq interrupts pending currently. 25 0 ro wmrpsipf wan mac receive process stopped interrupt pending for fiq when this bit is set, it indicates t hat the wan mac receive process stopped interrupt has the highest priority among all the fiq interrupts pending currently. 24 0 ro aberpf amba bus error response interrupt pending for fiq when this bit is set, it indicates that the amba bus error response interrupt has the highest priority among all the fiq interrupts pending currently. 23:20 0x00 ro reserved 19 0 ro wwupf wan wake-up interrupt pending for fiq when this bit is set, it indicates that the wan wake-up interrupt has the highest priority among all the fiq interrupts pending currently. 18 0 ro lwupf lan wake-up interrupt pending for fiq when this bit is set, it indicates that the lan wake-up interrupt has the highest priority among all the fiq interrupts pending currently. 17 0 ro lmtipf lan mac transmit interrupt pending for fiq when this bit is set, it indicates that the lan mac transmit interrupt has the highest priority among all the fiq interrupts pending currently. 16 0 ro lmripf lan mac receive interrupt pending for fiq when this bit is set, it indicates that the lan mac receive interrupt has the highest priority among all the fiq interrupts pending currently. 15 0 ro lmtbuipf lan mac transmit buffer unavailable interrupt pending for fiq when this bit is set, it indicates that the lan mac transmit buffer unavailable interrupt has the highest priority among all the fiq interrupts pending currently. 14 0 ro lmrbuipf lan mac receivet buffe r unavailable interrupt pending for fiq when this bit is set, it indicates that the lan mac receive buffer unavailable interrupt has the highest priority among all the fiq interrupts pending currently. 13 0 ro lmtpsipf lan mac transmit process stopped interrupt pending for fiq when this bit is set, it indicates t hat the lan mac transmit process stopped interrupt has the highest priority among all the fiq interrupts pending currently. 12 0 ro lmrpsipf lan mac receive pr ocess stopped interrupt pending for fiq when this bit is set, it indicates t hat the lan mac receive process stopped interrupt has the highest priority among all the fiq interrupts pending currently. 11 0x00 ro reserved 10 0 ro udpsif usb device interrupt pending for fiq when this bit is set, it indicates that u sb device interrrupt has the highest priority among all the fiq interrupts pending currently.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 207 m9999-031810-1.2 9 0 ro uhopsif usb host ohci interrupt pending for fiq when this bit is set, it indicates that usb host ohci interrrupt has the highest priority among all the fiq interrupts pending currently. 8 0 ro uhepsif usb host ehci interrupt pending for fiq when this bit is set, it indicates that usb host ehci interrrupt has the highest priority among all the fiq interrupts pending currently. 7 0 ro sdiopsif sdio interrupt pending for fiq when this bit is set, it indicates that the sdio interrupt has the highest priority among all the fiq interrupts pending currently. 6 0 ro factory reserved 5 0x00 ro reserved 4 0 ro ddrpf ddr interrupt pending for fiq when this bit is set, it indicates that the ddr interrupt has the highest priority among all the fiq interrupts pending currently. 3:0 0x00 ro reserved 2.20.26 interrupt pending highest priority register2 for fiq (inthpf2 offset 0xe264) the following table shows the register bit fields. bit field default value read/ write description 31:26 0x000 ro reserved. 25 0 rw u4lsepf uart4 line status error interrupt pending for fiq when this bit is set, it indicates that t he uart4 line status error interrupt has the highest priority among all the fiq interrupts pending currently. 24 0 rw u4rtlrpf uart4 receiver trigger level reached interrupt pending for fiq when this bit is set, it indicates that the uart4 line receiver trigger level reached interrupt has the highest priority among all the fiq interrupts pending currently. 23 0 rw u4tepf uart4 transmitter empty interrupt pending for fiq when this bit is set, it indicates that the uart4 transmitter empty interrupt has the highest priority among all the fiq interrupts pending currently. 22 0 rw u3 lsepf uart3 line status error interrupt pending for fiq when this bit is set, it indicates that t he uart3 line status error interrupt has the highest priority among all the fiq interrupts pending currently. 21 0 rw u3rtlrpf uart3 receiver trigger level reached interrupt pending for fiq when this bit is set, it indicates that the uart3 receiver trigger level reached interrupt has the highest priority among all the fiq interrupts pending currently. 20 0 rw u3tepf uart3 transmitter empty interrupt pending for fiq when this bit is set, it indicates that the uart3 transmitter empty interrupt has the highest priority among all the fiq interrupts pending currently. 19 0 rw u2lsepf uart2 line status error interrupt pending for fiq when this bit is set, it indicates that t he uart2 line status error interrupt has the highest priority among all the fiq interrupts pending currently. 18 0 rw u2rtlrpf uart2 receiver trigger level reached interrupt pending for fiq when this bit is set, it indicates that the uart2 receiver trigger level reached interrupt has the highest priority among all the fiq interrupts pending currently.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 208 m9999-031810-1.2 17 0 rw u2tepf uart2 transmitter empty interrupt pending for fiq when this bit is set, it indicates that the uart2 transmitter empty interrupt has the highest priority among all the fiq interrupts pending currently. 16 0 rw u1mpf uart modem interrupt pending for fiq when this bit is set, it indicates that the uart modem interrupt has the highest priority among all the fiq interrupts pending currently. 15 0 rw u1lsepf uart1 line status error interrupt pending for fiq when this bit is set, it indicates that t he uart1 line status error interrupt has the highest priority among all the fiq interrupts pending currently. 14 0 rw u1rtlrpf uart1 receiver trigger level reached interrupt pending for fiq when this bit is set, it indicates that t he uart1 line status error interrupt has the highest priority among all the fiq interrupts pending currently. 13 0 rw u1tepf uart1 transmitter empty interrupt pending for fiq when this bit is set, it indicates that the uart1 transmitter empty interrupt has the highest priority among all the fiq interrupts pending currently. 12 0 rw mdiopf mdio interrupt pending for fiq when this bit is set, it indicates that the mdio interrupt has the highest priority among all the fiq interrupts pending currently. 11 0 rw spipf spi interrupt pending for fiq when this bit is set, it indicates that the spi interrupt has the highest priority among all the fiq interrupts pending currently. 10 0 rw i2stpf i2s transmit interrupt pending for fiq when this bit is set, it indicates that the i2s interrupt has the highest priority among all the fiq interrupts pending currently. 9 0 rw i2srpf i2s receive interrupt pending for fiq when this bit is set, it indicates that i2s interrupt has the highest priority among all the fiq interrupts pending currently. 8 0 rw i2cpf i2c interrupt pending for fiq when this bit is set, it indicates that the i2c interrupt has the highest priority among all the fiq interrupts pending currently. 7 0 ro t1ipf timer 1 interrupt pending for fiq when this bit is set, it indicates that t he timer 1 interrupt has the highest priority among all the fiq interrupts pending currently. 6 0 ro t0ipf timer 0 interrupt pending for fiq when this bit is set, it indicates that t he timer 0 interrupt has the highest priority among all the fiq interrupts pending currently. 5 0 ro exti3pf external interrupt 3 pending for fiq when this bit is set, it indicates that the external interrupt 3 has the highest priority among all the fiq interrupts pending currently. 4 0 ro exti2pf external interrupt 2 pending for fiq when this bit is set, it indicates that the external interrupt 2 has the highest priority among all the fiq interrupts pending currently.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 209 m9999-031810-1.2 3 0 ro exti1pf external interrupt 1 pending for fiq when this bit is set, it indicates that the external interrupt 1 has the highest priority among all the fiq interrupts pending currently. 2 0 ro exti0pf external interrupt 0 pending for fiq when this bit is set, it indicates that the external interrupt 0 has the highest priority among all the fiq interrupts pending currently. 1 0 ro cctpf communications channel transmit pending for fiq when this bit is set, it indicates that the communications channel transmit has the highest priority among all the fiq interrupts pending currently. 0 0 ro ccrpf communications channel receive pending for fiq when this bit is set, it indicates that the communications channel receive has the highest priority among all the fiq interrupts pending currently. 2.20.27 interrupt pending highest priority register for irq (inthpi offset 0xe268) this register provides the interrupt in formation for the host to identify the pending interrupts with highest priority for irq (normal interrupt) note that it is possible to have more than one higest interrupts pending because of the same priority level. this register is provided to the host to quickly identif y and service the irq interrupt with the highest priority. this register is read only. the following table shows the register bit fields. bit field default value read/ write description 31 0 ro reserved 30 0 ro wmtipq wan mac transmit interrupt pending for irq when this bit is set, it indicates that the wan mac transmit interrupt has the highest priority among all the irq interrupts pending currently. 29 0 ro wmripq wan mac receive interrupt pending for irq when this bit is set, it indicates that the wan mac receive interrupt has the highest priority among all the irq interrupts pending currently. 28 0 ro wmtbuipq wan mac transmit buffer unavailable interrupt pending for irq when this bit is set, it indicates that the wan mac transmit buffer unavailable interrupt has the highest priority among all the irq interrupts pending currently. 27 0 ro wmrbuipq wan mac receivet buffe r unavailable interrupt pending for irq when this bit is set, it indicates that the wan mac receive buffer unavailable interrupt has the highest priority among all the irq interrupts pending currently. 26 0 ro wmtpsipq wan mac transmit process stopped interrupt pending for irq when this bit is set, it indicates that the wan mac transmit process stopped interrupt has the highest priority among all the irq interrupts pending currently. 25 0 ro wmrpsipq wan mac receive pr ocess stopped interrupt pending for irq when this bit is set, it indicates t hat the wan mac receive process stopped interrupt has the highest priority among all the irq interrupts pending currently. 24 0 ro aberpq amba bus error response interrupt pending for irq when this bit is set, it indicates that the amba bus error response interrupt has the highest priority among all the irq interrupts pending currently. 23:20 0x0 ro reserved 19 0 ro lwupfq lan wake-up interrupt pending for irq when this bit is set, it indicates that the lan wake-up interrupt has the highest priority among all the irq interrupts pending currently.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 210 m9999-031810-1.2 18 0 ro wwupfq wan wake-up interrupt pending for irq when this bit is set, it indicates that the wan wake-up interrupt has the highest priority among all the irq interrupts pending currently. 17 0 ro lmtipq lan mac transmit interrupt pending for irq when this bit is set, it indicates that the lan mac transmit interrupt has the highest priority among all the irq interrupts pending currently. 16 0 ro lmripq lan mac receive interrupt pending for irq when this bit is set, it indicates that the lan mac receive interrupt has the highest priority among all the irq interrupts pending currently. 15 0 ro lmtbuipq lan mac transmit buffer unavailable interrupt pending for irq when this bit is set, it indicates that the lan mac transmit buffer unavailable interrupt has the highest priority among all the irq interrupts pending currently. 14 0 ro lmrbuipq lan mac receivet buffe r unavailable interrupt pending for irq when this bit is set, it indicates that the lan mac receive buffer unavailable interrupt has the highest priority among all the irq interrupts pending currently. 13 0 ro lmtpsipq lan mac transmit pr ocess stopped interrupt pending for irq when this bit is set, it indicates t hat the lan mac transmit process stopped interrupt has the highest priority among all the irq interrupts pending currently. 12 0 ro lmrpsipq lan mac receive pr ocess stopped interrupt pending for irq when this bit is set, it indicates t hat the lan mac receive process stopped interrupt has the highest priority among all the irq interrupts pending currently. 11 0 ro reserved 10 0 ro udpsipq usb device interrupt pending for irq when this bit is set, it indicates that u sb device interrrupt has the highest priority among all the irq interrupts pending currently. 9 0 ro uhopsipq usb host o hci interrupt pending for irq when this bit is set, it indicates that usb host ohci interrrupt has the highest priority among all the irq interrupts pending currently. 8 0 ro uhepsipq usb host ehci interrupt pending for irq when this bit is set, it indicates that usb host ehci interrrupt has the highest priority among all the irq interrupts pending currently. 7 0 ro sdiopq sdio interrupt pending for irq when this bit is set, it indicates that the sdio interrupt has the highest priority among all the irq interrupts pending currently. 6 0 ro factory reserved 5 0 ro reserved 4 0 ro ddrpq ddr interrupt pending for irq when this bit is set, it indicates that the ddr interrupt has the highest priority among all the irq interrupts pending currently. 3:0 0x0 ro reserved
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 211 m9999-031810-1.2 2.20.28 interrupt pending highest priority register2 for irq (inthpi2offset 0xe26c) the following table shows the register bit fields. bit field default value read/ write description 31:26 0x000 ro reserved. 25 0 rw uart4lsepq uart4 line status error interrupt pending for irq when this bit is set, it indicates that t he uart4 line status error interrupt has the highest priority among all the irq interrupts pending currently. 24 0 rw u4rtlrpq uart4 receiver trigger level reached interrupt pending for irq when this bit is set, it indicates that the uart4 line receiver trigger level reached interrupt has the highest priority among all the irq interrupts pending currently. 23 0 rw u4tepq uart4 transmitter empty interrupt pending for irq when this bit is set, it indicates that the uart4 transmitter empty interrupt has the highest priority among all the irq interrupts pending currently. 22 0 rw u3lsepq uart3 line status error interrupt pending for irq when this bit is set, it indicates that t he uart3 line status error interrupt has the highest priority among all the irq interrupts pending currently. 21 0 rw u3rtlrpq uart3 receiver trigger level reached interrupt pending for irq when this bit is set, it indicates that the uart3 receiver trigger level reached interrupt has the highest priority among all the irq interrupts pending currently. 20 0 rw u3tepq uart3 transmitter empty interrupt pending for irq when this bit is set, it indicates that the uart3 transmitter empty interrupt has the highest priority among all the irq interrupts pending currently. 19 0 rw u2lsepq uart2 line status error interrupt pending for irq when this bit is set, it indicates that t he uart2 line status error interrupt has the highest priority among all the irq interrupts pending currently. 18 0 rw u2rtlrpq uart2 receiver trigger level reached interrupt pending for irq when this bit is set, it indicates that the uart2 receiver trigger level reached interrupt has the highest priority among all the irq interrupts pending currently. 17 0 rw u2tepq uart2 transmitter empty interrupt pending for irq when this bit is set, it indicates that the uart2 transmitter empty interrupt has the highest priority among all the irq interrupts pending currently. 16 0 rw u1mpq uart modem interrupt pending for irq when this bit is set, it indicates that the uart modem interrupt has the highest priority among all the irq interrupts pending currently. 15 0 rw u1lsepq uart1 line status error interrupt pending for irq when this bit is set, it indicates that t he uart1 line status error interrupt has the highest priority among all the irq interrupts pending currently. 14 0 rw u1rtlrpq uart1 receiver trigger level reached interrupt pending for irq when this bit is set, it indicates that t he uart1 line status error interrupt has the highest priority among all the irq interrupts pending currently. 13 0 rw u1tepq uart1 transmitter empty interrupt pending for irq when this bit is set, it indicates that the uart1 transmitter empty interrupt has the highest priority among all the irq interrupts pending currently. 12 0 rw mdiopq mdio interrupt pending for irq when this bit is set, it indicates that the mdio interrupt has the highest priority among all the irq interrupts pending currently.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 212 m9999-031810-1.2 11 0 rw spipq spi interrupt pending for irq when this bit is set, it indicates that the spi interrupt has the highest priority among all the irq interrupts pending currently. 10 0 rw i2stpq i2s transmit interrupt pending for irq when this bit is set, it indicates that the i2s interrupt has the highest priority among all the irq interrupts pending currently. 9 0 rw i2srpq i2s receive interrupt pending for irq when this bit is set, it indicates that i2s interrupt has the highest priority among all the irq interrupts pending currently. 8 0 rw i2cpq i2c interrupt pending for irq when this bit is set, it indicates that the i2c interrupt has the highest priority among all the irq interrupts pending currently. 7 0 ro t1ipq timer 1 interrupt pending for irq when this bit is set, it indicates that t he timer 1 interrupt has the highest priority among all the irq interrupts pending currently. 6 0 rw t0ipq timer 0 interrupt pending for irq when this bit is set, it indicates that t he timer 0 interrupt has the highest priority among all the irq interrupts pending currently. 5 0 ro exti3pq external interrupt 3 pending for irq when this bit is set, it indicates that the external interrupt 3 has the highest priority among all the irq interrupts pending currently. 4 0 ro exti2pq external interrupt 2 pending for irq when this bit is set, it indicates that the external interrupt 2 has the highest priority among all the irq interrupts pending currently. 3 0 ro exti1pq external interrupt 1 pending for irq when this bit is set, it indicates that the external interrupt 1 has the highest priority among all the irq interrupts pending currently. 2 0 ro exti0pq external interrupt 0 pending for irq when this bit is set, it indicates that the external interrupt 0 has the highest priority among all the irq interrupts pending currently. 1 0 ro cctpq communications channel transmit pending for irq when this bit is set, it indicates that the communications channel transmit has the highest priority among all the irq interrupts pending currently. 0 0 ro ccrpq communications channel receive pending for irq when this bit is set, it indicates that the communications channel receive has the highest priority among all the irq interrupts pending currently.. 2.21 timer registers 2.21.1 timer control register (tmcon offset 0xe400) the ksz8692mpb/KSZ8692XPB has two 32-bit timers(timer 0 and timer 1). when the timer expires, it generates a pulse on the i/o pins. these timer can operate in a very flexib le way. the host can control the timeout period as well as the pulse duration. the output signals are tout1 and tout0, respectively. these timers are enabled or disabled by this regsiter. interrupt can be generated by setting t he corresponding interrupt control registers. a timer generates a one-shot pulse with a preset timer clock duration whenever a timeout occurs. the duration of the one-shot pulse is also programmable by the host. this pulse consequently generates a time-out interrupt that is directly observable at the timers?s configured output pi n. the timer frequency is calculated as follows: f tout = f mclk / (timer data value + pulse data value)
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 213 m9999-031810-1.2 when the timer is enabled, it loads a data value to its count register and begins decrementing the count register value. when the timer expires, the corresponding to ut pin is then asserted. then it loads the pulse count value into the count register and starts decrementing. when the pulse data count reaches zero, the associated interrupt is asserted ( if enabled ), thetout pin is deasserted, and the timer data va lue is reloaded again for the next timeout. this process repeats until the timer is disabled. in our design, the frequency of mclk is 25mhz. the following table shows the register bit fields. bit field default value read/ write description 31:2 0x0 ro reserved 1 0 rw tout1e timer 1 enable when set, the timer 1 is enabled. timer process starts as soon as this bit is set. software should ensure correct timer c ount and pulse data values are preloaded before setting this bit. 0 0 rw tout0e timer 0 enable when set, the timer 0 is enabled. timer process starts as soon as this bit is set. software should ensure correct timer c ount and pulse data values are preloaded before setting this bit. 2.21.2 timer 1 timeout count register (t1tc offset 0xe404) this register controls the timeout count value to be preloaded to the down-counting register for timer 1. writing a zero to this register may result in unpredictable timer behavior. the following table shows the register bit fields. bit field default value read/ write description 31:0 -- rw tout1tc timer 1 timeout count this field specifies the durat ion that the tout1 pin is low in each timeout period. writing zero to this register may cause unpredictable behavior. 2.21.3 timer 0 timeout count register (t0tc offset 0xe408) this register controls the timeout count value to be preloaded to the down-counting register for timer 0. writing a zero to this register may result in unpredictable timer behavior. timer 0 can also be programmed as watchdog timer when the byte 0 of timeout count register is programmed as 8?hff. once it has been programmed as a watchdog timer, the value in timeout count register can never be re- programmed unless the timer is disabled first. in norma l system operation, the watc hdog timer will be periodically disabled by cpu before it expires. in case the watchdog timer expires (i ndicating system gets hung and cpu can not periodically come in to clear the timer by clearing the timer enable bit), a reset signal (active high) will be generated to reset the whole system. the following table shows the register bit fields. bit field default value read/ write description 31:0 0xffff_ff00 rw tout0tc timer 0 timeout count this field specifies the duration that the tout0 pi n is low in each timeout period. writing zero to this regi ster may cause unpredictable behavior. note that if the lowest byte is conf igured as 8?hff, timer 0 becomes watchdog timer.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 214 m9999-031810-1.2 2.21.4 timer 1 pulse count register (t1pd offset 0xe40c) this register controls the pulse data value to be preloaded to the down-counting register for timer 1. the tout1 pin output remains asserted at ?1? until the pul se counter reaches zero. writing a zero to this register may result in unpredictable timer behavior. the following table shows the register bit fields. bit field default value read/ write description 31:0 -- rw tout1pc timer 1 pulse count this field specifies the durat ion that the tout1 pin is high in each timeout period. writing zero to this register may cause unpredictable behavior. 2.21.5 timer 0 pulse count register (t0pd offset 0xe410) this register controls the pulse data value to be preloaded to the down-counting register for timer 0. the tout0 pin output remains asserted at ?1? until the pul se counter reaches zero. writing a zero to this register may result in unpredictable timer behavior. the following table shows the register bit fields. bit field default value read/ write description 31:0 -- rw tout0pc timer 0 pulse count this field specifies the durat ion that the tout0 pin is high in each timeout period. writing zero to this register may cause unpredictable behavior. 2.22 gpio registers 2.22.1 i/o port mode register (iopm offset 0xe600) this register controls the i/o pin input output mode. each i/o pin can be configured as input or output. note that some of the i/o pins are shared with the exte rnal interrupts and timer output. when these pins are configured for timer output, it overides the i/o port mode configuration. if the pins shared with external interrupt(gpio pins 3 to 0) are configured as output pins and are enabled for external/soft interrupt(e.g. port control register bit 15 is set to 1 enable the external/soft interrupt 3), cpu can generate a so ft interrupt by writing appropriate data(based on trigger mode defined in port control register) to the corresponding port data register. the following table shows the register bit fields. bit field default value read/ write description 31:20 0x0 ro reserved 19 0 rw iopm19 i/o port mode for gpio pin 19 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 18 0 rw iopm18 i/o port mode for gpio pin 18 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 17 0 rw iopm17 i/o port mode for gpio pin 17 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 16 0 rw iopm16 i/o port mode for gpio pin 16 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 215 m9999-031810-1.2 15 0 rw iopm15 i/o port mode for gpio pin 15 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 14 0 rw iopm14 i/o port mode for gpio pin 14 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 13 0 rw iopm13 i/o port mode for gpio pin 13 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 12 0 rw iopm12 i/o port mode for gpio pin 12 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 11 0 rw iopm11 i/o port mode for gpio pin 11 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 10 0 rw iopm10 i/o port mode for gpio pin 10 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 9 0 rw iopm9 i/o port mode for gpio pin 9 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 8 0 rw iopm8 i/o port mode for gpio pin 8 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 7 0 rw iopm7 i/o port mode for gpio pin 7 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 6 0 rw iopm6 i/o port mode for gpio pin 6 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. 5 0 rw iopm5 i/o port mode for gpio pin 5 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. note that gpio pin 5 is shared with timer 1 output. 4 0 rw iopm4 i/o port mode for gpio pin 4 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. note that gpio pin 4 is shared with timer 0 output. 3 0 rw iopm3 i/o port mode for gpio pin 3 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. note that gpio pin 3 is shared with external interrupt 3 input. 2 0 rw iopm2 i/o port mode for gpio pin 2 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. note that gpio pin 2 is shared wi th external interrupt 2 input.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 216 m9999-031810-1.2 1 0 rw iopm1 i/o port mode for gpio pin 1 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. note that gpio pin 1 is shared wi th external interrupt 1 input. 0 0 rw iopm0 i/o port mode for gpio pin 0 when set, the port is conf igured as an output pin. when reset, the port is configured as an input pin. note that gpio pin 0 is shared wi th external interrupt 0 input. 2.22.2 i/o port control register (iopc offset 0xe604) this register controls the usage of the shared i/o pins. the following table shows the register bit fields. bit field default value read/ write description 31:24 0x0 ro reserved 23 0 rw when set, gpio11 will be used for uart4 rts_n and gpio10 will be used for uart4 cts_n for h/w flow control s upport. gpio11 will be forced at output mode and gpio10 will be forced at input mode in this case. when reset, the shared gpio pin is used for normal gpio purpose. 22 0 rw when set, gpio9 will be used for uart3 rts_n and gpio8 will be used for uart3 cts_n for h/w flow control s upport. gpio9 will be forced at output mode and gpio8 will be forced at input mode in this case. when reset, the shared gpio pin is used for normal gpio purpose. 21 0 rw when set, gpio7 will be used for uart2 rts_n and gpio6 will be used for uart2 cts_n for h/w flow control s upport. gpio7 will be forced at output mode and gpio6 will be forced at input mode in this case. when reset, the shared gpio pin is used for normal gpio purpose. 20 0 rw ousbcken enable of observe usb signal s: 120 mhz clock, phy free clock, phy port 1 clock, phy port 2 clock, usb device clock, lsb of port 2 transmit data, lsb of port 1 transmit data, lsb of port 2 receive data, lsb of port 1 recieve data when set, the shared gpio pins (gpio[17:12], gpio[3:1]) are used for usb signals observation. gpio[17:12], gpioi[3 :1] will be forced at output mode. (factory reserved) when reset, the shared gpio pins are used for normal gpio purpose. 19 0 rw sleden sdio led enable when set, the shared gpio pin (gpio19) is used for sdio led. gpio19 will be forced at output mode. when reset, the shared gpio pin is used for normal gpio purpose 18 0 rw obinten observe internal interrupt enable when set, the shared gpio pin (gpio18) is used to monitor the internal interrupt (fiq and irq) to cpu. gpio18 will be forced at output mode. when reset, the shared gpio pin is used for normal gpio purpose. 17 0 rw iotim1en gpio pin for timer 1 enable when set, the shared gpio pin (gpio5) for timer 1 is used for the timer. when reset, the shared gpio pin for timer 1 is used for normal gpio purpose. 16 0 rw iotim0en gpio pin for timer 0 enable when set, the shared gpio pin (gpio4) for timer 0 is used for the timer. when reset, the shared gpio pin for timer 0 is used for normal gpio operation.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 217 m9999-031810-1.2 15 0 rw ioeint3en gpio[3] pin for ex ternal/soft interrupt 3 enable. this bit has higher priority than bit[20] (ousbcken) when set, the shared gpio[3] pin (ext3) for external interrupt request 3 is used for the interrupt. when reset, the shared gpio[3] pin (ext3) for external interrupt request 3 is used for normal gpio operation. 14:12 000 rw ioeint3tm gpio[3] pin for external /soft interrupt 3 trigger mode this field is used to configure the tr igger mode for external interrupt 3. 000= level detection (active low) 001= level detection (active high) 01x= rising edge detection 10x= falling edge detection 11x= both edge detection 11 0 rw ioeint2en gpio[2] pin for ex ternal/soft interrupt 2 enable. this bit has higher priority than bit[20] (ousbcken) when set, the shared gpio[2] pin (ext2) for external interrupt request 2 is used for the interrupt. when reset, the shared gpio[2] pin (ext2) for external interrupt request 2 is used for normal gpio operation. 10:8 000 rw ioeint2tm gpio[2] pin for external /soft interrupt 2 trigger mode this field is used to configure the tr igger mode for external interrupt 2. 000= level detection (active low) 001= level detection (active high) 01x= rising edge detection 10x= falling edge detection 11x= both edge detection 7 0 rw ioeint1en gpio[1] pin for ex ternal/soft interrupt 1 enable. this bit has higher priority than bit[20] (ousbcken) when set, the shared gpio[1] pin (ext1) for external interrupt request 1 is used for the interrupt. when reset, the shared gpio[1] pin (ext1) for external interrupt request 1 is used for normal gpio operation. 6:4 000 rw ioeint1tm gpio pin for external /soft interrupt 1 trigger mode this field is used to configure the tr igger mode for external interrupt 1. 000= level detection (active low) 001= level detection (active high) 01x= rising edge detection 10x= falling edge detection 11x= both edge detection 3 0 rw ioeint0en gpio[0] pin for exte rnal/soft interrupt 0 enable when set, the shared gpio[0] pin (ext0) for external interrupt request 0 is used for the interrupt. when reset, the shared gpio[0] pin (ext0) for external interrupt request 0 is used for normal gpio operation. 2:0 000 rw ioeint0tm gpio pin for external /soft interrupt 0 trigger mode this field is used to configure the tr igger mode for external interrupt 0. 000= level detection (active low) 001= level detection (active high) 01x= rising edge detection 10x= falling edge detection 11x= both edge detection
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 218 m9999-031810-1.2 2.22.3 i/o port data register (iopd offset 0xe608) this register contains the one-bit read values for i/o ports that are configured as input port, and one-bit write value for i/o ports that are configured as output port. bi ts[19:0] of the 20-bit i/o port register value correspond directly to the 20 i/o pins, gpio[19:0]. the following table shows the register bit fields. bit field default value read/ write description 31:20 0x0 ro reserved 19:0 -- rw iopd i/o port data value the values reflect the signal level on t he respective i/o port pins. when the ports are configured as output port, the bit reflec ts the port write value. when the port is configured as input port, the bit reflects the port read value. 2.23 i2c registers 2.23.1 global control (offset 0xe800): i2c_gcr bit field name read/ write description default 31:24 reserved ro reserved 0x00 23:16 timeout rw number of bit times allowed to complete transaction before aborting. 0x10 15 enable i2c stop rw enable stop bit generation after ev ery data cycle, read or write. 1 : enable stop bit generation 0 : disable stop bit generation 0 14:10 reserved ro reserved 0x00 9:1 bit period rw bit period in units of ahb clock period * 8. ie for ahb clock = 200mhz (5 ns period) ? bit period unit = 40ns default: 166mhz ahb clock, 400khz data rate actual data rate = 399.04khz 0x033 0 i2c enable rw enable i2c to perform data transfers. i2c must be disabled before changing the bit period. 0 2.23.2 i2c address (offset 0xe804): i2c_ar bit field name read/ write description default 31:24 reserved ro reserved 0x00 23:20 number of bytes to write rw number of bytes to read for each transaction (start/stop pair). 0000 ? reserved 0001 ? 1 byte write ? 1000 ? 8 bytes write 1001 ? reserved ? 1111 ? reserved 0x1
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 219 m9999-031810-1.2 19:16 number of bytes to read rw number of bytes to read for each transaction if it?s greater than 1, a sequential read is issued. (start/stop pair). 0000 ? reserved 0001 ? 1 byte read ? 1000 ? 8 bytes read 1001 ? reserved ? 1111 ? reserved 0x1 11 10-bit i2c address rw use 10-bit device address for i2c transaction. 0 10:8 address (extended) rw write device address [9:7] used for 10-bit extended i2c addressing. - 7:1 address (standard) rw write device address [6:0] used for standard i2c addressing. - 0 read/nwrite rw 1 = i2c read transaction 0 = i2c write transaction 0 2.23.2 i2c start command (offset 0xe808): i2c_scr bit field name read/ write description default 31:1 reserved ro reserved 0x0000_000 0 0 start/done command rw start/done command. write a 1 to start i2c transaction. cleared to 0 when i2c transaction is completed. 0 2.23.3 i2c status (offset 0xe80c): i2c_sr bit field name read/ write description default 31 scl line status ro the current value of the scl signal - 30 sda line status ro the current value of the sda signal - 29:17 reserved ro reserved 0x0000 16 data transfer done ro 1 = burst data transfer was comp leted. all programmed burst data has be transferred. can verify how many bytes has been transferred with this register?s bi ts [11:8] for read and [15:12] for writes. these values should ma tch the programmed burst length value. 0
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 220 m9999-031810-1.2 15:12 number of bytes written ro number of bytes that were writt en out from wdr1/0 registers. this field is valid when bit 16 is set, and bits[6:0] are not set in the register. this field specifies how many bytes has been written out when the burst transaction stopped. the burst transaction stops when the burst is done or when one of the timeout error conditions occurs. this field is cleared after reading. 0x0 = reserved 0x1 = 1 byte valid: wdr0[7:0] 0x2 = 2 bytes valid: wdr0[15:0] ? 0x7 = 7 bytes valid: {wdr1[23:0], wdr0[31:0]} 0x8 = 8 bytes valid: {wdr1, wdr0} 0x9 ? 0xf = reserved 15:12 11:8 number of bytes read ro number of bytes available to be read out from rdr1/0 registers. this field is valid when any of the following bits in this register are set: [15] or [3:0]. this field specifies how many bytes has been read when the burst transaction stopped. the burst transaction stops when the burst is done or when one of the timeout error conditions occurs. this field is cleared after reading. 0x0 = reserved 0x1 = 1 byte valid: rdr0[7:0] 0x2 = 2 bytes valid: rdr0[15:0] ? 0x7 = 7 bytes valid: {rdr1[23:0], rdr0[31:0]} 0x8 = 8 bytes valid: {rdr1, rdr0} 0x9 ? 0xf = reserved - 7 reserved ro reserved 0 6 wr data error ro 1 = wr data was corrupted by i2c slave driving sda during data transmission. this bit is cleared after reading. 5 start bit timeout ro 1 = sda timeout error during t he start bit caused by i2c slave pulling sda low longer than the progr ammed time out value. this bit is cleared after reading. 0 4 stop bit timeout ro 1 = sda timeout error during the stop bit caused by i2c slave pulling sda low longer than the progr ammed time out value. this bit is cleared after reading. 0 3 data phase timeout ro 1 = data timeout error caused by i2c slave wait state exceeding programmed time out value during the data phase. this bit is cleared after reading. 0 2 address phase timeout ro 1 = address timeout error caused by i2c slave wait state exceeding programmed time out value during the address phase. this bit is cleared after reading. 0 1 no data ack error ro 1 = write data byte did not receive an ack. this bit is valid only for write cycles. this bit is cleared after reading. 0 0 no address ack error ro 1 = no ack after address phase. this bit is cleared after reading. 0
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 221 m9999-031810-1.2 2.23.4 read data0 (offset 0xe810): i2c_rdr0 bit field name read/ write description default 31:24 read data byte 3 ro read 4 th data byte - 23:16 read data byte 2 ro read 3 rd data byte - 15:8 read data byte 1 ro read 2 nd data byte - 7:0 read data byte 0 ro read 1 st data byte - 2.23.5 read data1 (offset 0xe814): i2c_rdr1 bit field name read/ write description default 31:24 read data byte 7 ro read 8 th data byte - 23:16 read data byte 6 ro read 7 th data byte - 15:8 read data byte 5 ro read 6 th data byte - 7:0 read data byte 4 ro read 5 th data byte - 2.23.6 write data0 (offset 0xe818): i2c_wdr0 bit field name read/ write description default 31:24 write data byte 3 ro write 4 th data byte - 23:16 write data byte 2 ro write 3 rd data byte - 15:8 write data byte 1 ro write 2 nd data byte - 7:0 write data byte 0 ro write 1 st data byte - 2.23.7 write data1 (offset 0e8x1c): i2c_wdr1 bit field name read/ write description default 31:24 write data byte 7 ro write 8 th data byte - 23:16 write data byte 6 ro write 7 th data byte - 15:8 write data byte 5 ro write 6 th data byte - 7:0 write data byte 4 ro write 5 th data byte -
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 222 m9999-031810-1.2 2.23.8 debug (offset 0xe820): i2c_debug bit field name read/ write description default 31:3 reserved ro reserved 0x0000_000 0 2 enable scl / sda outputs rw = 1 enable scl and sda output. bits [1:0] can control scl and sda i/o directly. use in c onjunction with i2c_ar[31:30]. 0 1 scl output rw scl output. when enabled (bit [2] = 1) directly drives the bit value onto scl. 1 0 sda output rw sda output. when enabled (bit [2] = 1) directly drives the bit value onto sda. 1 2.24 spi registers 2.24.1 spi operations the master spi controls data transfers to and from the slave. the spi master driv es the chip select (cs) and the serial clock (spck) to the slave. after enabli ng the spi the core writes data to the spi_tdr (transmit data register). a data transfer begins when the spi_tdr writes to transmit buffer. when new data is ava ilable in the transmit buffer, the spi continues to transfer data. the received data is written to receive buffer. when the receiv e buffer reaches its threshold or the timer is expired, the rdrdy flag is set. if the receive buffer is full, t he receive data buffer full (rdbf) flag is set. note: as long as rdbf flag is set, no new data is loaded to receive data buffer. the user has to read the spi_rdr (from receive buffer) and to read interrupt stat us register (spi_isr) to clear rdbf flag. the delay between the active cs (dlybcs) and the delay between each data transfer (dlybct) can be programmed. all data transfer characteristics are programmed in spi_csr (chip select register). figure 1 and figure 2 show the operation of spi. chip select the spi master device drives the chip select (cs) line. the value on the cs pin at the end of each transfer can be read in the spi_rdr (receive data register). the cs signal active state is programmable in spi_csr. if the cs active state is logic low (equal to zero), the cs signal is l ogic high (equal to one) before and after each transfer. clock generation and transfer delays the spi clock (spck) is generated by dividing the sy stem clock (sysclk) by a value between 16 and 65536. the divisor is defined in the chip select registers ( spi_csr). the spi baud rate is the rate of spck. spr[2:0] divide ck by sysclk = 166mhz sysclk = 125mhz sysclk = 50mhz 000 16 10.375 mhz 7.813 mhz 3.125 mhz 001 32 5.188mhz 3. 906mhz 1.5626mhz 010 64 2.594 mhz 1.953 mhz 781.25 khz 011 128 1.297mhz 976. 6khz 390.625khz 100 256 648 khz 488 khz 195.312 khz 101 1024 162 khz 122 khz 48.828 khz 110 8192 20.26khz 15. 26khz 6.104khz 111 65536 2.53khz 1.907khz 763hz table 1. spi clock rates
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 223 m9999-031810-1.2 figure 1 shows a chip select transfer change and consec utive transfers on the same cs. three delays can be programmed to modify the transfer waveforms: ? dlybcs: delay between two cs enable is programmable by writing the field dlybcs in the chip select registers (spi_csr). allows inserti on of a delay between release of one chip select and before assertion of a new one. ? dlybct: delay between consecutive tr ansfers is programmable by writi ng the field dlybct in the spi_csr. allows insertion of a delay between tw o transfers occurring on the same cs. ? dlybs: delay between cs active and 1 st spck is programmable by writing the field dlybs. allows the start of spck to be delayed until after the chip select has been asserted. these delays allow the spi to be adapted to the inte rfaced peripherals and their speed and bus release time. programmable delays figure 1. programmable delays data transfer four modes are used for spi data transfers. these modes co rrespond to combinations of a pair of parameters called clock polarity (cpol) and clock phase (cpha) that determine the edges of the clock signal on which the data are driven and sampled. each of the two parameters has two possible st ates, resulting in four possi ble combinations that are incompatible with one another. thus a master/slave pair must use the same parameter pair values to communicate. table 2 shows the four modes and corresponding parameter settings. spi mode cpol cpha 0 0 0 1 0 1 2 1 0 3 1 1 table 2. spi bus protocol mode spi one frame ? ? dlybct dlybs dlybct dlybcs cs spck dlybct
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 224 m9999-031810-1.2 figure 2 and figure 3 show examples of data transfers: figure 2. spi transfer format (ckpha=1, 8 bits per transfer) figure 3. spi transfer format (ckpha=0, 8 bits per transfer) x x spck mode = 1 spck mode = 3 mosi miso cs spck mode = 2 miso mosi cs spck mode= 0 2 1 3 4 5 6 7 8 2 1 3 4 5 6 7 8 msb msb
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 225 m9999-031810-1.2 2.24.1 control register (spi_ctr) (offset 0xe900) bit(s) name description default r/w 31 software reset swrst 0 = no effect. 1 = reset the spi. 0 r/w 30 spi enable spien 0 = disables the spi. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. 1 = enables the spi to transfer and receive data. 0 r/w 29:2 reserved ignore when read. 0 ro 1 wait 1st rdy for rx 0 = disabled, does not check fo r 1st rdy before reading rx frame length byte. 1 = enabled, checks rdy (f rom micrf800) before reading rx frame length byte. note spi_tdr[12] must be a 1, micrel mode, for this feature to be enabled. 0 r/w 0 wait 1st rdy for tx 0 = disabled, does not check for 1st rdy before writing tx frame length byte. 1 = enabled, checks rdy (fro m micrf800) before writing tx frame length byte. note spi_tdr[12] must be a 1, micrel mode, for this feature to be enabled. 0 r/w note: micrf800 is for interface to micrel part number mi crf800. bits designated as micrf are applicable to this interface. 2.24.2 receive data register (spi_rdr) (offset 0xe904) bit(s) name description default r/w 31:16 received data rd[15:0] the received data is the data pointing to read pointer in receive buffer. 0 ro 15:0 chip select value rd_cs normal mode (tdr.micrf=0): [15] indicates the value on the cs pin at the end of a transfer. [14:0] reserved ignore when read. micrel mode (tdr.micrf=1): [15:0] receive data. the w hole spi_rdr becomes a 32-bit data registers. 0 ro 2.24.3 transmit data register (spi_tdr) (offset 0xe908) bit(s) name description default r/w 31:16 td[15:0] transmit data, written to transmit buffer 0 r/w 15 cs_end 0 = after this transmission command, keep cs asserted. 1 = after this transmission command, de-assert the cs. 0 r/w 14 hiz (1) micrf=0 0 = there is output driving mosi pin, and no data clock in to the receive data buffer. 1 = set high impedance in mosi pin when process the first character in transmit buffer. there is no data output driving the mosi. there is receive data clock in to the receive data buffer. (2) micrf=1 reserved. 0 r/w
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 226 m9999-031810-1.2 13 hiz_ext (1) micrf=0 0 = there is output driving mosi pin, and no data clock in to receive data buffer. 1 = set high impedance in mosi pin when spi goes to character extend state. this field is applied in read operation of a 3-wir ed spi slave device. (2) micrf=1 in micrel mode, this bit indicates tx/rx mode. 0 = tx mode. 1 = rx mode. 0 r/w 12 micrf 0 = normal spi mode. 1 = indicates the spi changes to micrel mode to support micrf interface after finishing this command. 0 r/w 11:8 bits[3:0] (1) micrf=0 programmable bits per transfer the bits field determines the number of data bits transferred. values greater than 8 should not be used. bits per transfer = 8 + bits[3:0] (2) micrf=1 reserved. 0 r/w 7:0 cext[7:0] (1) micrf=0 characters extend. indicate number characters of clocks to be generated after td[15:0] transmi ssion. if (cext==0), it is a write operation. otherwi se, a read operation will be applied after the td[15:0] is tr ansmitted. if (cext > 1), the read operation should be in burst read mode (2) micrf=1 if (hiz_ext==0) this field indicates tx frame length. if (hiz_ext==1) ignore this field 0 r/w 2.24.4 micrel mode transmit data register (spi_mcr) (offset 0xe90c) bit(s) name description default r/w 31:0 mctd[31:0] transmit data, written to transmit buffer this field is valid when spi_tdr[12] is asserted. 0 r/w 2.24.5 buffer status register (spi_bfr) (offset 0xe910) bit(s) name description default r/w 31:24 rx_length micrel mode rx length. ignored when micrf=0; 0 ro 23:22 reserved ignore when read. 0 ro 21 rb_udr indicates a fatal error, w hen receive buffer empty and apb keep reading data from buffer. 0 ro 20:16 rb_lvl[4:0] these bits indicate data left in receive buffer. 0 ro 15:6 reserved ignore when read. 0 ro 5 tb_ovr indicates a fatal error, when transmit buffer full and apb keep writing data to buffer. 0 ro 4:0 tb_lvl[4:0] these bits indicate data left in transmit buffer. 0 ro
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 227 m9999-031810-1.2 2.24.6 interrupt status register (spi_isr) (offset 0xe914) bit(s) name description default r/w 31 rb_full receive data buffer full. 0 = no buffer full has been detected since the last read of isr. 1 = buffer full has occurred since the last read of isr. 0 ro 30 rdrdy receive data ready. 0 = no data ready in rbuf since last read of isr. 1 = rbuf reaches its threshold or the timer is expired. 0 ro 29 xrdy rdy interrupt from external input pin. 0 ro 28 tb_full transmit data buff full. 0 = no full has been detected since the last read of isr. 1 = buffer full has occurred since the last read of isr. 0 ro 27 tb_th transmit buffer level is lower than the threshold. 0 ro 26:0 reserved ignore when read. 0 ro 2.24.7 interrupt enable register (spi_ier) (offset 0xe918) bit(s) name description default r/w 31 rdbf_en 0 = receive data buffer full interrupt disable 1 = receive data buffer full interrupt enable 0 r/w 30 rdrdy_en 0 = receive data ready interrupt disable 1 = receive data ready interrupt enable 0 r/w 29 xrdy_en 0 = external rdy input interrupt disable 1 = external rdy input interrupt enable 0 r/w 28 tdbf_en 0 = transmit data buffer full interrupt disable 1 = transmit data buffer full interrupt enable 0 r/w 27 tbth_en 0 = transmit buffer threshold interrupt disable 1 = transmit buffer threshold interrupt enable 0 r/w 26:0 reserved ignore when read. 0 ro 2.24.8 chip select register (spi_csr) (offset 0xe91c) bit(s) name description default r/w 31 spck polarity cpol 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. 0 r/w 30 spck phase ckpha 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ckpha determines which edge of spck causes data to change and which edge causes dat a to be captured. ckpha is used with cpol to produce the required clock/data relationship between master and slave devices. figure 1 and figure 2 show the operation. 0 r/w
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 227 m9999-031810-1.2 29:27 spr[2:0] spck clock rate selection. 000: divided sysclk by 16. 001: divided sysclk by 32. 010: divided sysclk by 64. 011: divided sysclk by 128. 100: divided sysclk by 256. 101: divided sysclk by 1024. 110: divided sysclk by 8192. 111: divided sysclk by 65536. 0 r/w 26 acs active level of chip select 0 = active state value of cs is logic level zero. 1 = active state value of cs is logic level one. 0 r/w 25:24 reserved ignore when read. 0 ro 23:20 tbuf_th[3:0] transmit buffer threshold. 4?h8 r/w 19:16 rbuf_th[3:0] receive buffer threshold. 4?h8 r/w 15:13 reserved ignore when read. 0 ro 12 dlybs delay before spck. this field defines the delay from cs valid to the first valid spck transition. 0 = the cs valid to spck transition is ? spck clock period. 1 = the cs valid to spck transition is 1 spck clock period. 0 r/w 11:8 dlybct[3:0] delay between consecutive transfers this field defines the delay between two consecutive transfers without removing the cs. the delay is always inserted after each transfer and before removing the cs if needed. the inserted delays are equal to (1 + clybct[3:0] ) spck cycles. 0 r/w 7:0 dlybcs[7:0] delay between chip selects. this field defines the delay from cs inactive to another cs active. 0 r/w 2.25 miscellaneous registers 2.25.1 device id register (did offset 0xea00) this read-only register hol ds a 16-bit device id. the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 15:0 0x8692 ro device id
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 228 m9999-031810-1.2 2.25.2 revision id register (rid offset 0xea04) this register holds a 4-bit sub- device id and a 4-bit revision id. the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:5 001b 010b ro sub-device id. indicates th is device is KSZ8692XPB (pci support). sub-device id. indicates this device is ksz8692mpb (pci support). 4:0 00010b ro revision id 2.25.3 ddr controller diagnostic register (ddrdiag offset 0xea10) the following table shows the register bit fields. bit field default value read/ write description 31 0 rw ddr srefresh_enter command when this parameter is written with a ?b1, the dram device(s) will be placed in self- refresh mode. for this, the current burst for the current transaction (if any) will complete, all banks will be closed, the self-refresh command will be issued to the dram, and the clock enable signal will be deasserted. the sy stem will remain in self-refresh mode until this parameter is written with a ?b0. t he dram devices will return to normal operating mode after the self-refresh exit time (txs r) of the device and any dll initialization time for the dram is reached. the memory controller will resume processing of the commands from the interruption point. this will ove rride the register programming inside the ddr controller. to disable self-refresh again after a srefresh_enter, the user will need to clear this to ?b0. ? ?b0 = disable self-refresh mode. ? ?b1 = initiate self-refresh of the dram devices. 30:4 0x0 ro reserved 3 0 ro ddr refresh-in-process status indicates that the ddr controller is execut ing a refresh command. this is asserted when a refresh command is sent to the dram devices and remains asserted until the refresh command has completed. 2 0 ro ddr dll lock status indicates the dll has locked. 1 0 ro ddr q-almost-full status indicates that the queue has reached the value set in the q_fullness parameter. 0 0 ro ddr controller busy status status signal from the memory controller. this will only be low when the memory controller is not reading data, writ ing data or processing a command. 2.25.3 usb phy control register (upc offset 0xea20) the following table shows the register bit fields. bit field default value read/ write description 31:12 0x0 ro reserved 11 0x0 rw ovrcp, over current polarity 1: positive sense over current 0: negative sense over current
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 229 m9999-031810-1.2 10 0x0 rw siddq, static siddq te st setup, will shut down t he power in usb ananlog partion. 9 0x0 rw vatest_enb, which enables usb_analog_test pin output 8:1 0x0 ro reserved 0 0x0 rw usb_device_detect_vbus, set this bit to one will trigger the usb device controller to release the reset and start the normal function mode 1: enable usb device enter function mode 0: disable the usb device 2.25.5 usb phy test control register ( upt offset 0xea24) the following table shows the register bit fields. bit field default value read/ write description 31:14 0x0 ro reserved 13 0x0 rw usb phy analog test data out seletion 12:9 0x0 rw usb phy analog tests address 8:1 0x0 rw usb phy analog test data in 0 0x0 rw usb phy analog test interface test_clk 2.25.6 usb phy test status register ( ups offset 0xea28) the following table shows the register bit fields. bit field default value read/ write description 31:8 0x0 ro reserved 7:4 0x0 ro usb ph y test_data_out_1[3:0] 3:0 0x0 ro usb phy test_data_out_0[3:0] 2.25.7 pll diagnostic control register ( pdc offset 0xea2c) the following table shows the register bit fields. bit field default value read/ write description 31:21 0x0 ro pll oper ation mode control 20:11 0x0 rw pllb test control 10:1 0x0 rw plla test control 0 0x0 rw pll bandgap select 2.25.8 nand flash busy status ( nflbs offset 0xea40) the following table shows the register bit fields. bit field default value read/ write description 31:2 0x0 ro reserved 1 - ro nand flash bank1 busy status 1 ? bank1 busy signal from nand flash device is active 0 ? bank1 busy signal from nand flash device is not active 0 - ro nand flash bank0 busy status 1 ? bank0 busy signal from nand flash device is active 0 ? bank0 busy signal from nand flash device is not active
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 230 m9999-031810-1.2 2.25.9 spare register ( sr offset 0xea50) the following table shows the register bit fields. bit field default value read/ write description 31:16 0x0 ro reserved 15:2 0x0 rw for spare registers purpose 1 0x0 rw when set, it will pass the checksum check at receive side and skip the checksum generation at transmit side for ipv6 udp packet w/ fragment extension header. when cleared, it will perform checksum oper ation based on confi guration and doesn?t care whether it?s a fragment packet or not. 0 0x0 rw when set, it will pass the filtering for ipv6 udp packet w/ udp checksum equal to zero. when cleared, it will drop ipv6 udp packet w/ udp checksum equal to zero. 2.26 i2s registers 2.26.1 i2s control (offset 0xeb00): i2s_cr bit(s) name r/w description default 31:23 reserved ro 0 22 left justified rw 0 = i2s timing 1 = left justified timing 0 21:20 bit select rw 00: 16 bit wide audio data 01: 18 bit wide audio data 10: 20 bit wide audio data 11: 24 bit wide audio data 0 19:16 bclk divisor rw bclk frequency = mclk frequency / (divisor+1). 0 15:13 reserved ro 0 12 rx enable rw enable i2s to receive. when disabled, rx function will be reset. 2 mclk cycles needed to change this bit. i.e., once sw changed this bit, it should keep it unchanged for at least 2 mclk cycles. 0 11:10 reserved ro 0 9:8 rx interrupt threshold rw interrupt will be triggered when rx buffer counter hit the threshold: 0: >= half of the rx buffer has valid data 1: >= ? of the rx buffer has valid data 2: >= ? of the rx buffer has valid data 3: reserved 0 7:5 reserved ro 0 4 tx enable rw enable i2s to transmit. when disabled, tx function will be reset. 2 mclk cycles needed to change this bit. i.e., once sw changed this bit, it should keep it unchanged for at least 2 mclk cycles. 0 3:2 reserved ro 0 1:0 tx interrupt threshold rw interrupt will be triggered when tx buffer counter hit the threshold: 0: >= half of the tx buffer has not been used 1: >= ? of the tx buffer has not been used 2: >= ? of the tx buffer has not been used 3: reserved 0 note: if both rx and tx enable is cleared to 0, there will be no bclk and lrclk toggle.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 231 m9999-031810-1.2 2.26.2 i2s tx status (offset 0xeb04): i2s_tsr bit(s) name r/w description default 31:11 reserved 0 10 tx hit ro tx threshold is hit. 0 9 tx overrun ro tx buffer overrun. sw writes tx buffer when it is full. cleared after read. 0 8 tx underrun ro tx buffer underrun. tx when buffer is empty. cleared after read. 0 7:6 reserved ro 0 5:0 tx valid counter ro i2s tx buffer valid c ounter, i.e., how many entries in the buffer are available for write. 0 2.26.3 i2s rx status (offset 0xeb08): i2s_rsr bit(s) name r/w description default 31:11 reserved 0 10 rx hit rx threshold is hit. 0 9 rx overrun ro rx buffer overrun. rx when buffer is full. cleared after read. 0 8 rx underrun ro rx buffer underrun. sw r ead rx buffer when is empty. cleared after read. 0 7:6 reserved ro 0 5:0 rx counter ro i2s rx buffer counter, i.e., how many data words in the buffer are ready to read 0 2.26.4 i2s data (offset 0xeb0c): i2s_dr bit(s) name r/w description default 31:0 audio data rw write this register will cause the data wr itten to the tx buffer. left channel and right channel data shoul d be interleaved. so, the 1 st write data belongs to left channel, and the 2 nd one is for right channel, then repeated till tx disabled. read this register will get the dat a from the rx buffer. also, left channel and right channel data are interleaved. the 1 st read data is from left channel, the 2 nd one is from right channel, then repeated till rx disabled. the data format is left justified, i.e., data[31:0] = { audio data, padding 0s} -
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 232 m9999-031810-1.2 2.27 sta registers 2.27.1 configuration register this configuration register gives the software capability to change the mdc period based on apb clock speed, as well as the management frame option. sta_cfg:: (offset 0xec00) bit(s) name r/w description default 31 auto_poll rw auto poll option. when de-asserted, the sta is working at manual mode. it is the software?s responsibility to issue mdio transactions by writing command register. when asserted, the sta is working at the auto-polling mode. it will poll phy status register every 1024 mdc cycles. 0x0 30:18 reserve ro reserved 0x0 17 mdc_shutdown rw optional mdc shutdown. when this bit is set to one by software, the mdc output clock will be turned off if there is no transaction on mdc/mdio interface. 0: mdc keeps running as long as apb clock is running. 1: mdc runs only when a transaction is proceeding on mdc/mdio interface. mdc is turned off when the transaction is completed. 0x0 16 pre_suppresion rw preamble suppression. the software sets this bit to one when it determines that all the phy devices are able to accept management frames with preamble suppressed. 0: send management frames with 32-bit preamble. 1: send management frames without preamble bits. 0x0 15:9 reserved ro reserved. 0x0 8:1 clk_dividend rw the mdc out put frequency is calculated as: f mdc = f apb / (clk_dividend * 2) let?s take apb clock 200 mhz as typical, and choose 16 as the default value of this register, this results in a mdc frequency of 6.25mhz. 0x10 0 mdio_enable rw if asserted, enable mdio management interface to perform data transfers. it must be disabled before changi ng the clk_dividend. the software shall not disable this bit when the sta_status.status field is not idle. the user shall read the sta_st atus register before updating this bit. violation on this rule may cause unexpected behavior on the mdc/mdio interface. 0x1 table 1. sta configuration register description 2.27.2 installed phy register the installed phy register defines t he valid phy addresses in the system. sta_installed_phy:: (offset 0xec04) bit(s) name r/w description default 31:16 reserve ro reserved 0x0 15 phy1_vld rw if asserted, phy1 is installed and phy1_addr is a valid address assigned in the system. 14:13 reserve ro reserved 0x0 12:8 phy1_addr rw the physical address assigned to phy1 0x0 7 phy0_vld rw if asserted, phy0 is installed and phy0_addr is a valid address assigned in the system. 0x0 6:5 reserve ro reserved 0x0 4:0 phy0_addr rw the physical address assigned to phy0 0x0 table 2. installed phy register description
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 233 m9999-031810-1.2 2.27.3 interrupt enable register the interrupt enable register maintains an enable bit for each interrupt event. the software can enable or disable interrupts triggered by the associated events. sta_int_enable:: (offset 0xec08) bit(s) name r/w description default 31:7 reserve ro reserved 0x0 6 phy_aerr_enable rw the interrupt enable for its associated interrupt event. 0x0 5 proc_terr_enable rw the interrupt enable for its associated interrupt event. 0x0 4 phy1_dn_chg_enable rw the interrupt enabl e for its associated interrupt event. 0x0 3 phy1_up_chg_enable rw the interrupt enabl e for its associated interrupt event. 0x0 2 phy0_dn_chg_enable rw the interrupt enabl e for its associated interrupt event. 0x0 1 phy0_up_chg_enable rw the interrupt enabl e for its associated interrupt event. 0x0 0 cpu_cmplt_enable rw the interrupt enable for its associated interrupt event. 0x0 table 3. interrupt enable register description 2.27.4 interrupt event register the interrupt event register captures t he events that assert the interrupt signal. all fields shall be cleared after register read. sta_int_event:: (offset 0xec0c) bit(s) name r/w description default 31:7 reserve ro reserved 0x0 6 phy_aerr ro the phy address error. if asserted, the software has issued a transaction to undefined phy address against sta_installed_phy register. no transaction will be issued in this case. this bit is cleared after cpu read. 0x0 5 proc_terr ro the procedure transaction error. if asserted, the software has issued a new transaction start co mmand before the status field goes back to idle. no transaction will be issued in this case. this bit is cleared after cpu read. 0x0 4 phy1_dn_chg ro this event indicates a link change from up to down on phy1. this bit is cleared after cpu read. 0x0 3 phy1_up_chg ro this event indicates a link change from down to up on phy1. this bit is cleared after cpu read. 0x0 2 phy0_dn_chg ro this event indicates a link change from up to down on phy0. this bit is cleared after cpu read. 0x0 1 phy0_up_chg ro this event indicates a link change from down to up on phy0. this bit is cleared after cpu read. 0x0 0 cpu_cmplt ro this event indicate s that cpu issued transaction has been completed. this bit is cleared after cpu read. 0x0 table 4. interrupt event register description
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 234 m9999-031810-1.2 2.27.5 command register the apb bus updates this register to define the commands to be issued over sta management interface. sta_command:: (offset 0xec10) bit(s) name r/w description default 31:18 reserved ro reserved 0x0 17:16 burst_size rw the software can tri gger a burst of transactions over sta management interface with one command by specifying the command burst size. 2?b00: one transaction; 2?b01: two transactions; 2?b10: three transactions; 2?b11: four transactions. note that during burst transactions, the phy address remains the same, while register address is incremented by 1 in the next transaction. 0x0 15:11 reserved ro reserved. 0x0 10:6 regaddr rw 5-bit phy register address. each phy can implement at most 32 mii registers, including mandatory registers and optional registers. 0x0 5:1 phyaddr rw 5-bit phy address. each sta is able to connect up to 32 unique phy devices. for every transaction, the sta has to identity the specific phy to be accessed. 0x0 0 opcode rw read/write operation to be executed over sta management interface. 0: write operation; 1: read operation. 0x0 table 5. sta command register description 2.27.6 control register sta_control:: (offset 0xec14) bit(s) name r/w description default 31:1 reserved ro reserved 0x0 0 start wo start command. write a one to start a sta management transaction when the transaction status field is id le. the start command is ignored and an error status is indicated in sta_status.status field if the transaction status field is not idle. it is always read as 0. 0x0 table 6. sta control register description
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 235 m9999-031810-1.2 2.27.7 status register sta_status:: (offset 0xec18) bit(s) name r/w description default 31:4 reserved ro reserved 0x0 [3:2] op_size ro the burst size of last completed transaction. this field is only valid when the status field is wdone or rdone. 2?b00: one transaction; 2?b01: two transactions; 2?b10: three transactions; 2?b11: four transactions. the software uses this informati on to retrieve valid read data from access data (0-1) registers. 0x0 1:0 status ro the transaction status. 2?b00: idle, no transaction is in progress. 2?b01: busy, a transaction is in progress. this field shall remain in busy state until the transaction has been completed on mdc/mdio interface. 2?b10: wdone, a write transacti on has been finished. this field switches to idle automatically only when this status register has been read. 2?b11: rdone, a read transaction has been finished. this field switches to idle automatically only when ? this status register has been read; ? the valid access data (0-1) registers have been read back through apb bus. 0x0 table 7. sta status register description 2.27.8 access data 0 register this register holds the access data to the first and the second mii registers. the apb bus has to configure this register first before starting a write transaction. sta_data0:: (offset 0xec1c) bit(s) name r/w description default 31:16 word1 rw the 2 nd access data word. 0x0 15:0 word0 rw the 1 st access data word 0x0 table 8. sta data 0 register description 2.27.9 access data 1 register this register holds the access data to the third and the fourth m ii registers. the apb bus has to configure this register first before starting a write transaction only if the software wants to issues a burst of 3 or 4 transactions. sta_data1:: (offset 0xec20) bit(s) name r/w description default 31:16 word3 rw the 4 th access data word. 0x0 15:0 word2 rw the 3 rd access data word 0x0 table 9. sta data 1 register description
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 236 m9999-031810-1.2 2.28 mib counters 2.28.1 port 0 mib counters (offset 0xed00 - edff) offset counter name description 0xed00 rxbyte rx octet count including bad pkts 0xed04 rxundersizepkt rx undersize pkts w/ good crc 0xed08 rxfragments rx fragment pkts w/ bad crc, symbol errors or alignment errors 0xed0c rxoversize rx oversize pkts w/ good crc (max: 2000 bytes) 0xed10 rxjabbers rx pkts longer than 2000b w/ either crc errors, alignment errors, or symbol errors. (depends on max packet size setting). 0xed14 rxsymbolerror rx pk ts w/ invalid data symbol and legal packet size. 0xed18 rxcrcerror rx pkts wi thin (64,2000) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0xed1c rxalignmenterror rx pkts within (64,2000) bytes w/ a non-integr al number of bytes and a bad crc (upper limit depends on max packet size setting). 0xed20 rxcontrol8808pkts the number of mac control frames received by a port with 88-08h in ethertype field. 0xed24 rxpausepkts the number of pause frames receiv ed by a port. pause frame is qualified with ethertype (88-08h), da, control opcode (00-01), data length (64b min), and a valid crc 0xed28 rxbroadcast rx good broadcast pkts (not including errored broadcast pkts or valid multicast pkts) 0xed2c rxmulticast rx good multicat pk ts (not including mac control frames, errored multicast pkts or valid broadcast pkts) 0xed30 rxunicast rx good unicast packets 0xed34 rx64octets total rx pkts (bad pkts included) that were 64 octets in length 0xed38 rx65to127octets total rx pkts (bad pkts included) that are between 65 and 127 octets in length 0xed3c rx128to255octets total rx pk ts (bad pkts included) that are between 128 and 255 octets in length 0xed40 rx256to511octets total rx pkts (bad pkts included) that are between 256 and 511 octets in length 0xed44 rx512to1023octets total rx pkts (bad pkts included) that are between 512 and 1023 octets in length 0xed48 rx1024to1521octets total rx pkts (bad pkts included) that are bet ween 1024 and 1521 octets in length. 0xed4c rx1522to2000octets total rx pk ts (bad pkts included) that are between 1522 and 2000 octets in length. 0xed50 rx2001maxoctets total rx pkts (bad pkts included) that are greater than or equal to 2001 octets in length. 0xed54 txbyte tx good octet count, including pause pkts 0xed58 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a pkt 0xed5c txpausepkts the number of pause frames transmitted by a port 0xed60 txbroadcastpkts tx good broadcast pkts (not in cluding errored broadcast or valid multicast pkts) 0xed64 txmulticastpkts tx good multicast pkts (not incl uding errored multicast pkts or valid broadcast pkts) 0xed68 txunicastpkts tx good unicast pkts 0xed6c txdeferred tx pkts by a port for which t he 1st tx attempt is delayed due to the busy medium 0xed70 txtotalcollision tx total collision, half duplex only 0xed74 txexcessivecollision a count of frames for which tx fails due to excessive collisions 0xed78 txsinglecollision successfully tx frames on a por t for which tx is inhibited by exactly one collision 0xed7c txmultiplecollision successfully tx frames on a por t for which tx is inhibited by more than one collision table 10. port 0 mib counter direct memory offsets note: a per port mib counter will be cleared after it is accessed.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 237 m9999-031810-1.2 format of port 0 mib counters (31 entries) bit(s) name r/w description default 31-0 counter values ro counter value 0 2.28.2 port 1 mib counters offset counter name description 0xedc0 rxbyte rx (default) octet count including bad pkts 0xedc4 rxundersizepkt rx undersize pkts w/ good crc 0xedc8 rxfragments rx fragment pkts w/ bad crc, symbol errors or alignment errors 0xedcc rxoversize rx oversize pkts w/ good crc oversize frame is greater than 9216 bytes if jumbo frame select (bit10 of lan mac misc control register (lemc offset 0x8020) ) is set. otherwise, it?s 2000 bytes. 0xedd0 rxjabbers rx pkts longer than 2000b w/ either crc errors, alignment errors, or symbol errors. (depends on max packet size setting). 0xedd4 rxsymbolerror rx pkts w/ in valid data symbol and legal packet size. 0xedd8 rxcrcerror rx pkts within (64,2000) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0xeddc rxalignmenterror rx pkts with in (64,2000) bytes w/ a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting). 0xede0 rxcontrol8808pkts the number of mac control frames received by a port with 88-08h in ethertype field. 0xede4 rxpausepkts the number of pause frames received by a port. pause frame is qualified with ethertype (88-08h), da, control opcode (00-01), data length (64b min), and a valid crc 0xede8 rxbroadcast rx good broadcast pk ts (not including errored broadcast pkts or valid multicast pkts) 0xedec rxmulticast rx good multicat pk ts (not including mac control frames, errored multicast pkts or valid broadcast pkts)
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 238 m9999-031810-1.2 0xedf0 rxunicast rx good unicast packets 0xedf4 rx64octets total rx pkts (bad pkts included) that were 64 octets in length 0xedf8 rx65to127octets total rx pk ts (bad pkts included) that are between 65 and 127 octets in length 0xedfc rx128to255octets total rx pk ts (bad pkts included) that are between 128 and 255 octets in length 0xee00 rx256to511octets total rx pkts (bad pkts included) that are between 256 and 511 octets in length 0xee04 rx512to1023octets total rx pkts (bad pkts included) that are between 512 and 1023 octets in length 0xee08 rx1024to1521octets total rx pkts (bad pkts included) that are bet ween 1024 and 1521 octets in length. 0xee0c rx1522to2000octets total rx pkts (bad pkts included) that are bet ween 1522 and 2000 octets in length. 0xee10 rx2001to9216octets total rx pkts (bad pkts included) that are bet ween 2001 and 9216 octets in length. 0xee14 rx9217tomaxoctets total rx pkts (bad pkts included) that are great er than or equal to 9217 octets in length. 0xee18 txbyte tx good octet count, including pause pkts 0xee1c txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a pkt 0xee20 txpausepkts the number of pause frames transmitted by a port 0xee24 txbroadcastpkts tx good broadcast pkts (not including errored broadcast or valid multicast pkts) 0xee28 txmulticastpkts tx good multicast pkts (not incl uding errored multicast pkts or valid broadcast pkts) 0xee2c txunicastpkts tx good unicast pkts 0xee30 txdeferred tx pkts by a port for which the 1st tx attempt is delayed due to the busy medium 0xee34 txtotalcollision tx total collision, half duplex only 0xee38 txexcessivecollision a count of frames for which tx fails due to excessive collisions 0xee3c txsinglecollision successfully tx frames on a por t for which tx is inhibited by exactly one collision 0xee40 txmultiplecollision successfully tx frames on a por t for which tx is inhibited by more than one collision table 11. port 1 mib counter direct memory offsets format port 1 mib counters (31 entries) bit(s) name r/w description default 31-0 counter values ro counter value 0
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 239 m9999-031810-1.2 2.29 nand flash control registers (0x0000 - 0xffff) the control registers are mapped to 64kbyte of user defined space. the input addr ess from bit 15:0 to provide 16kword of addressable spaces. each word is 4 bytes long (32 bits). each register must be accessed as a 32-bit entity. individual byte access is not allowed. each register is mapped to a 32- bit word in the memory space. data register is mapped to multiple locations in the lower half of the register address space. the same data register is accessed regardless of the address used to access the data register. this arrangement a llows user to generate burst access to the data register. the address mapping is the following: register address(15:0) description 0x0000 to 0x7fff data register 0x8000 command register 0x8004 index register 0x8008 status register 0 0x800c reserved 0x8010 id register 0 0x8014 reserved 0x8018 id register 1 0x801c reserved 0x8020 id register 2 0x8024 reserved 0x8028 id register 3 0x802c reserved 0x8030 reserved 0x8034 reserved 0x8038 reserved 0x803c to 0x8044 reserved 0x8048 extended index register 0x804c timing register 0 0x8050 timing register 1 0x8054 configuration register 0x8058 to 0xffff reserved table 12. register map 2.29.1 register access the nand flash controller and all its registers are accessed from the ahb bus. the controller follows the ahb bus protocol as a slave device. please refer the ahb bus specification on ahb bus protocol description. 2.29.2 nand flash data register (nfld offset 0x0000 ? 0x7fff ) the data register is used according to the access procedure de scribed in following sections of this document. it is used to read and write data to the flash. the address of the data to be accessed in the flash is determined by the value programmed in the index register. the address used to access data register is irrelevant. multiple addresses are assigned to the data register so that user can use bur st access to access sequential data in the flash.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 240 m9999-031810-1.2 the following table shows the bit fields of nfld register. bit field default value read/ write description 31:0 0x0 rw nfld nand flash data register 2.29.3 nand flash command register ( nflc offset 0x8000 ) the least significant 8 bits of the command register resemb les the actual command value s ent to the flash device. the remaining bits further modify the command when necessary . the following are the valid command register values: the following table shows the bit fields of nflc register. bit field default value read/ write description 31:0 0x0 rw nflc nand flash command register bit 31:8 (hex) bit 7:0 description 000000 00 read command. the actual command issued to the core such as ?00?, ?01? or ?50? will be determined by the core based on the index register. 000000 to 000001 ff reset. bit 9 to 8 defines the bank number to be reset. only one bank is reset for each command. 000000 to 000001 90 read id. bit 9 to 8 defines the bank number to be read. only one bank is read for each command. 000000 80 page program 000000 10 page program confirm 000000 to 000001 70 read status. bit 9 to 8 defines the bank number to be read. only one bank is read for each command. 000000 60 block erase 000000 d0 erase confirm 000000 ee turn off ce signal to the flash after read access. this is not a command to the flash but a command to the controller. table 13. command register
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 241 m9999-031810-1.2 2.29.4 nand flash index register ( nfli offset 0x8004 ) index register (0x8004) and ext ended index register(0x8048) toget her form a 40-bit address register with index register being the lsb and extended index being the m sb. this register contains the addr ess (or starting address for sequential access) of the flash device to be accessed. the index r egister is the address that will be used to access the nand flash. the relationship between index register and address depends on the total width of the nand flash device(s). if only one 8-bit nand flash is used, the index should be the by te address of the location to be accessed. since a 32-bit data is accessed each time, the nand flash controller issues 4 sequential read to fetch a 32-bit word. in this case the 2lsb of the index register should be ?0?..the following tabl es list the address bit usage for small and large block nand flash. the number in each table cell indicates the bits tak en from the index register to form the address for the nand flash device. the following table shows the bit fields of nfli register. bit field default value read/ write description 31:0 - rw nand flash address bits [31:0]] 8 bits 16 bits nand flash size page column bank page column bank 64mbit 23:12 11:0 25: 24 22:11 10:0 24:23 128mbit 24:12 11:0 26: 25 23:11 10:0 25:24 256mbit 25:12 11:0 27: 26 24:11 10:0 26:25 512mbit 26:12 11:0 28: 27 25:11 10:0 27:26 1gbit 27:12 11:0 29: 28 26:11 10:0 28:27 2gbit 28:12 11:0 30: 29 27:11 10:0 29:28 4gbit 29:12 11:0 31: 30 28:11 10:0 30:29 8gbit 30:12 11:0 32: 31 29:11 10:0 31:30 table 14. address bit usage for large block nand flash column nand flash size page 8-bit 16-bit spare column bank 64mbit 22:9 8:0 7:0 25 24:23 128mbit 23:9 8:0 7:0 26 25:24 256mbit 24:9 8:0 7:0 27 26:25 512mbit 25:9 8:0 7:0 28 27:26 1gbit 26:9 8:0 7:0 29 28:27 2gbit 27:9 8:0 7:0 30 29:28 4gbit 28:9 8:0 7:0 31 30:29 8gbit 29:9 8:0 7:0 32 31:30 table 15. address bit usage for small block nand flash
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 242 m9999-031810-1.2 2.29.5 nand flash status register ( nfls offset 0x8008 ) this is a read only register. when this r egister is read from the user interface, the controller issues read command to one of the flash banks according to bit 9:8 of the command regist er. each flash device has 8 bits of status. individual bit definition of the status is described in the flash device data sheet. the memory cont roller reads the status bits from the status register and arrange them as the following: the following table shows the bit fields of nfls register. bit field default value read/ write description 31:24 - ro reserved 23:16 - ro reserved 15:8 - ro status of chip 1 that contains data bit 15:8 7:0 - ro status of chip 0 that contains data bit 7:0 2.29.6 reserved ( offset 0x800c ) bit field default value read/ write description 31:0 - ro reserved. 2.29.7 nand flash id0 register ( nflid0 offset 0x8010 ) this is a read only register. when this r egister is read from the user interface, the controller issues read command to one of the flash banks according to bit 9:8 of the command register. the following table shows the bit fields of nflid0 register. bit field default value read/ write description 31:24 - ro reserved 23:16 - ro reserved 15:8 - ro maker code of chip 1 that contains data bit 15:8 7:0 - ro maker code of chip 0 that contains data bit 7:0 2.29.8 reserved ( offset 0x8014 ) bit field default value read/ write description 31:0 - ro reserved.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 243 m9999-031810-1.2 2.29.9 nand flash id1 register ( nflid1 offset 0x8018 ) this is a read only register. when this r egister is read from the user interface, the controller issues read command to one of the flash banks according to bit 9:8 of the command register. the following table shows the bit fields of nflid1 register. bit field default value read/ write description 31:24 - ro reserved 23:16 - ro reserved 15:8 - ro device code of chip 1 that contains data bit 15:8 7:0 - ro device code of chip 0 that contains data bit 7:0 2.29.10 reserved (offset 0x801c ) bit field default value read/ write description 31:0 - ro reserved. 2.29.11 nand flash id2 register (nflid2 offset 0x8020 ) this is a read only register. when this r egister is read from the user interface, the controller issues read command to one of the flash banks according to bit 9:8 of the command register. the following table shows the bit fields of nflid2 register. bit field default value read/ write description 31:24 - ro reserved 23:16 - ro reserved 15:8 - ro third byte id of chip 1 that contains data bit 15:8 7:0 - ro third byte id of chip 0 that contains data bit 7:0 2.29.12 reserved (offset 0x8024 ) bit field default value read/ write description 31:0 - ro reserved. 2.29.13 nand flash id3 register (nflid3 offset 0x8028 ) this is a read only register. when this r egister is read from the user interface, the controller issues read command to one of the flash banks according to bit 9:8 of the command register. the following table shows the bit fields of nflid3 register. bit field default value read/ write description 31:24 - ro reserved 23:16 - ro reserved 15:8 - ro multi plane code of chip 1 t hat contains data bit 15:8 7:0 - ro multi plane code of chip 0 t hat contains data bit 7:0
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 244 m9999-031810-1.2 2.29.14 reserved (offset 0x802c ? 0x8044 ) bit field default value read/ write description 31:0 - ro reserved. 2.29.15 nand flash extended index register (nflei offset 0x8048 ) extended index register forms the upper 8-bit of the nand flash address. it is used only if 8-gbit or larger nand flash devices are used. if 8-gbit 8-bit wide nand flash is used, bit 32:31 forms the bank decode (chip enable, ce#). bit 32 is bit 0 of the extended index register. when less than 33 bit address bit is needed, the extended index register should be programmed once to all ?0?. the following table shows the bit fields of nflei register. bit field default value read/ write description 31:8 - ro reserved. 7:0 - rw nflei nand flash extended index 8 msb of the nand flash extended address 2.29.16 nand flash timing control 0 register (nfltc0 offset 0x804c ) the following table shows the bit fields of nfltc0 register. each bit field represents number of system clock period. bit field default value read/ write description 31:24 - rw cle, ce# and ale hold time relative to we# rising edge. 23:16 - rw re# (read) pulse width 15:8 - rw we# (write) pulse width 7:0 - rw setup time for cle, ce# and ale to command (we# and re#) 2.29.17 nand flash timing control 1 register (nfltc1 offset 0x8050 ) the following table shows the bit fields of nfltc1 register. each bit field represents number of system clock period. bit field default value read/ write description 31:24 - rw we# (write) rising edge to ry/by# (busy) falling edge 23:16 - rw ry/by# (busy) rising edge to read pulse falling edge 15:8 - rw re# (read) pulse high time 7:0 - rw we# (write) pulse high time 2.29.18 nand flash configuration register (nflc offset 0x8054 ) the following table shows the bit fields of nflc register. bit field default value read/ write description 31:9 - ro reserved. 8 - rw nand flash type 0 = small block 1 = large block
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 245 m9999-031810-1.2 7:6 - rw number of active banks (ce#) in cascade. 00 = 1 bank 01 = 2 banks 10 = reserved 5:4 - rw number of nand flash in parallel for combined data width, not including ecc 00 = 1 nand flash 01 = 2 nand flash 10 = reserved 3 - rw individual nand flash data with 0 = 8 bits 1 = 16 bits 2:0 - rw nand flash size 000 = 64mbit 001 = 128mbit 010 = 256mbit 011 = 512mbit 100 = 1gbit 101 = 2gbit 110 = 4gbit 111 = 8gbit 2.29.19 access procedure this section describes the acce ss procedures to the nand flash. 2.29.19.1 single read 1. write 0x00 to command register 2. write to index register 3. read data register * 4. when read data register, the core will retry the read, issue the read request to flash. after flash data is read, core will accept the retry request and provide data. 5. write 0xee to command register to turn off chip enable * note: * mark indicates this st ep triggers action to the flash. 2.29.19.2 sequential read 1. write 0x00 to command register 2. write to index register 3. read data register * 4. when read data register, the core will retry the read, issue the read request to flash. after flash data is stored, core will accept the retry request and provide data. 5. read data register again. the core will read sequential data from flash. * 6. write 0xee to command register to turn off chip enable. * 2.29.19.3 single write 1. write 0x80 to command register 2. write to index register 3. write to data register, the core will accept the write data. * 4. write page program confirm (0x10) to command register. * 2.29.19.4 sequential write 1. write 0x80 to command register 2. write to index register
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 246 m9999-031810-1.2 3. write to data register, the core will accept data and write to flash * 4. write to data register, the core will accept data and write to flash in sequential address. * 5. write page program confirm (0x10) to command register. * 2.29.19.5 block erase 1. write 0x60 to command register 2. write to index register 3. write erase confirm command (0xd0) to command register. * 2.29.19.6 read status 1. write 0x70 to command register. * 2. read status register, first 2 byte status result is available in status register 0. 2.29.19.7 read id 1. write 0x90 to command register. * 2. read id0 register to get maker code. maker code of first 2 bytes are in id register 0. 3. read id1 to id3 to get remaining id fields. 2.29.19.8 reset 1. write 0xff to command register. *
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 247 m9999-031810-1.2 3.0 host communication this chapter describes the descriptor lists and data buffers , which are collectively called the host communication area, that manage the actions and status related to buffer management. commands and signals that control the functional operation of the ksz8692mpb/KSZ8692XPB are also described. the ksz8692mpb/KSZ8692XPB and the driver communicate through the two data structures: system configuration registers (scrs) and descriptor lists and data buffers. note: all unused bits the data structure in this chapter are reserved and should be written by the driver as zero. 3.1 descriptor lists and data buffers the ksz8692mpb/KSZ8692XPB transfers received data frames to the receive buffer in host memory and transmits data from the transmit buffe rs in host memory. descriptors that reside in the host memory act as pointers to these buffers. there are two descriptor lists; one for receive and one for transmit for each mac dma(wan and lan). the base address of each list for wan is written on wtdlb, and w rdlb, respectively. the base address of each list for lan is written on ltdlb, and lrdlb, respectively. a descr iptor list is forward linked. the last descriptor may point back to the first entry to create a ring st ructure. descriptors are chained by setting the next address to next buffer in both the receive and transmit descriptors. the descriptor lists reside in the host physical memory address space. each pointer points to one buffer and the second pointer points to the next descriptor. this enables the greatest flexibility for the host to chain any data buffers with discontinuous memory location. this elimi nates processor-intensive tasks such as memory copying from the host to memory. a data buffer contains of either an entire frame or part of a frame, but it cannot exceed a single frame. buffers contain only data; buffer status is maintained in the descrip tor. data chaining refers to frames that span multiple data buffers. data chaining can be enabled or disabled. da ta buffers reside in host physical memory space. the descriptor structures for wan and lar are identical. fo r simplicity, they are both collectively referred to as rdes0-3, and tdes0-3 for receive and transmit. 3.2 receive descriptors (rdes0-rdes3) receive descriptors and buffers addresses must be word ali gned. each receive descriptor provides one frame buffer, one byte count field, as well as control and status bits. the following table shows the rdes0 register bit fields. bit field default value 31 own own bit when set, indicates that the descriptor is ow ned by the ksz8692mpb/KSZ8692XPB. when reset, indicates that the descriptor is owned by the host. the ksz8692mpb/KSZ8692XPB clears this bit either when it completes the frame reception or when the buffers t hat are associated with this descriptor are full. 30 fs first descriptor when set, indicates that this descriptor contains the first buffer of a frame. if the buffer size of the first buffer is 0, t he next buffer contains t he beginning of the frame. 29 ls last descriptor when set, indicates that the buffer pointed by this descriptor is the last buffer of the frame.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 248 m9999-031810-1.2 28 es error summary indicates the logical or of the following rdes0 bits: crc error frame too long runt frame mii error ip checksum error this bit is valid only when last descriptor is set. 27:25 ces ip checksum error summary 000: no checksum error 001: ip header checksum error 010: tcp checksum error 011: udp checksum error 100: icmp checksum error 101: reserved 110: reserved 111: reserved this bit is valid only when last descriptor is set. 24 ccnc ip header/tcp/udp/icmp checksum checking not completed when set, it indicates the enabled checksum checking proc ess is not completed due to either the scale is beyond h/w?s capability or an unexpected event occurs. when cleared, it indicates either no checksum checking is required or the checksum checking is completed for this packet. 23:22 checksum not completed cause: 00: none 01: ipv4/ipv6 fragment packet 10: ipv6 encapsulating security included 11: unrecognized next header detected [this bit is only valid when ccnc (bit24) is set.] 21:20 nbs this is to inform cpu how many bytes is required to shift from the starting buffering address to grab the 1st byte of the packet when ip header dw alignment f eature is active. the vaule will be zero when ip header dw alignment feature is disabled or the received packet is not an ip packet. 00: no shift 01: n/a 10: shift 2 bytes 11: shift 3 bytes 19 re report on mii error when set, indicates that a receive error in the physi cal layer was reported during the frame reception. 18 tl frame too long when set, indicates that the frame length exceeds the maximum size of 2000 bytes or 9kb if jumbo frame feature is enable. this bit is valid only when last descriptor is set. note: frame too long is only a frame length indication and does not cause any frame truncation.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 249 m9999-031810-1.2 17 rf runt frame when set, indicates that this frame was damaged by a collision or premature termi nation before the collision window has passed. runt frames are passed on t he host only if the pass bad frames bit is set. 16 ce crc error wen set, indicates that a crc erro r occurred on the received frame. this bit is valid only when last descriptor is set. 15 ft frame type when set, indicates that the frame is an ethernet-type frame (frame lengt h field is greater than 1500 bytes). when clear, indicates that the frame is an ieee 802.3 frame. this bit is not valid for runt frames. this bit is valid only when last descriptor is set. 14 hi priority frame 0: low priority 1: high priority 13:0 fl frame length indicates the length, in bytes, of the received frame, including the crc. this field is valid only when last descrip tor is set and descrip tor error is reset. note: frame length bit field is from bit13 to bit0 at lan port due to 9kb jumbo frame support. the wan port frame length bit field is from bit11 to bit0 since the maximum packet length support is 2kb at wan port. the following table shows the rdes1 register bit fields. bit field description 31:26 reserved 25 rer receive end of ring when set, indicates that the descriptor list r eached its final descriptor. the ksz8692mpb/KSZ8692XPB returns to the base address of the lis t, thus creating a descriptor ring. 24:14 reserved 13:0 rbs receive buffer size indicates the size, in bytes, of the receive data buffer. if the field is 0, the ksz8692mpb/KSZ8692XPB ignores this buffer and move s to the next descriptor. the buffer size must be a multiple of 4. the following table shows the rdes2 register bit fields. bit field description 31:0 buffer address indicates the physical memory address of the buffer. the buffer address must be word aligned. the following table shows the rdes3 register bit fields. bit field description 31:0 next descriptor address indicates the physical memory address of the next descr iptor in the descriptor ring. the buffer address must be word aligned.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 250 m9999-031810-1.2 3.3 transmit descriptors (tdes0-tdes3) transmit descriptors must be word aligned. each descriptor pr ovides one frame buffer, one byte count field, as well as control and status bits. the following table shows the tdes0 register bit fields. bit field description 31 own own bit when set, indicates that the descriptor is owned by the ksz8692mpb/KSZ8692XPB. when cleared, indicates that the descriptor is owned by the host. the ksz8692mpb/KSZ8692XPB clears this bit either when it completes the frame transmission or when the buffer allocated in the descriptor is empty. the ownership bit of the first descriptor of the fr ame should be set after all subsequent descriptors belonging to the same frame have been set. this avoi ds a possible race condition between the ksz8692mpb/KSZ8692XPB fetching a descriptor and the driver setting an ownership bit. 30:0 reserved the following table shows the tdes1 register bit fields. bit field description 31 ic interrupt on completion when set, the ksz8692mpb/KSZ8692XPB set transmit interrupt after the present frame has been transmitted. it is valid only when last segment is set. 30 fs first segment when set, indicates that the buffer cont ains the first segment of a frame. 29 ls last segment when set, indicates that the buffer cont ains the last segment of a frame. 28 ipckg ip checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct ip checksu m for outgoing frames that contains ip protocol header. the ksz8692mpb/KSZ8692XPB supports only standard ip header, i.e. ip with 20 byte header. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the ip checksum generate bit in the transmit mode register is not set. this bit should be always set for multiple-segment packets. 27 tcpckg tcp checksum generate when set, the ksz8692mpb/KSZ8692XPB w ill generate correct tcp checksu m for outgoing frames that contains ip and tcp protocol header. the ksz8692mpb/KSZ8692XPB supports standard and non- standard ip header size. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the tcp checksum generate bit in the transmit mode register is not set. this bit should be always set for multiple-segment packets. 26 udpckg udp checksum generate when set, the ksz8692mpb/KSZ8692XPB w ill generate correct udp checksu m for outgoing frames that contains ip and udp protocol header. the ksz8692mpb/KSZ8692XPB supports standard and non- standard ip header size. when this feature is used, add crc bit in the transmit mode register should always be set. this bit is used as a per-packet control when the udp checksum generate bit in the transmit mode register is not set. 25 ter transmit end of ring when set, indicates that the descriptor poi nter has reached its final descriptor. the ksz8692mpb/KSZ8692XPB returns to the base addre ss of the list, forming a descriptor ring.
ksz8692mpb/KSZ8692XPB registration description integrated networking and communications controller march 2010 251 m9999-031810-1.2 24 icmpckg icmp checksum generate when set, the ksz8692mpb/KSZ8692XPB will generate correct icmp checksu m for outgoing frames that contains ip and icmp protocol header. the ksz8692mpb/KSZ8692XPB supports standard and non- standard ip header size. when this feat ure is used, add crc bit in the tr ansmit mode register should always be set. this bit is used as a per-packet control when the icmp checksum generate bit in the transmit mode register is not set. 23:14 reserved 13:0 tbs transmit buffer size indicates the size, in bytes, of the transmit dat a buffer. if this field is 0, the ksz8692mpb/KSZ8692XPB ignores this buffer and move s to the next descriptor. note: buffer size bit field is from bit13 to bit0 at lan port due to 9kb jumbo frame support. the wan buffer size bit field is from bit11 to bit0 since t he maximum packet length support is 2kb at wan port. note: do not use bit 24 icmpckg icmp for icmp ipv6 fragmented packets (software to generate the checksum) the following table shows the tdes2 register bit fields. bit field description 31:0 buffer address indicates the physical memory address of the buffer. there is no limitation on the tr ansmit buffer address alignment. the following table shows the tdes3 register bit fields. bit field description 31:0 next descriptor address indicates the physical memory address of the next descr iptor in the descriptor ring. the buffer address must be word aligned. micrel, inc. 2180 fortune dri ve san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circ uitry and specifications at any time without notification to the customer. micrel products are not designed or authoriz ed for use as components in life support appli ances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or systems are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expect ed to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages re sulting from such use or sale. ? 2008 micrel, incorporated.

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